Slide 1Last Time: Virtual MemoryA System Using Virtual AddressingLast Time: Address TranslationTodayAddress Translation: Page HitAddress Translation: Page FaultSpeeding up Translation with a TLBTLB HitTLB MissSimple Memory System ExampleSimple Memory System Page TableSimple Memory System TLBSimple Memory System CacheAddress Translation Example #1Address Translation Example #2Address Translation Example #3SummaryTodayAllocating Virtual PagesAllocating Virtual PagesTodayMulti-Level Page TablesA Two-Level Page Table HierarchyTranslating with a k-level Page TableTodayLinux Organizes VM as Collection of “Areas”Linux Page Fault HandlingMemory MappingUser-Level Memory MappingUser-Level Memory Mappingmmap() Example: Fast File CopyExec() RevisitedFork() RevisitedMemory System SummaryTodayIntel P6 (Bob Colwell’s Chip, CMU Alumni)P6 Memory SystemReview of AbbreviationsOverview of P6 Address TranslationP6 2-level Page Table StructureP6 Page Directory Entry (PDE)P6 Page Table Entry (PTE)Representation of VM Address SpaceP6 TLB TranslationP6 TLBTranslating with the P6 TLBP6 TLB TranslationTranslating with the P6 Page Tables (case 1/1)Translating with the P6 Page Tables (case 1/0)Translating with the P6 Page Tables (case 1/0, cont.)Translating with the P6 Page Tables (case 0/1)Translating with the P6 Page Tables (case 0/0)Translating with the P6 Page Tables (case 0/0, cont.)P6 L1 Cache AccessL1 Cache AccessSpeeding Up L1 Accessx86-64 Pagingx86-64 PagingCarnegie MellonIntroduction to Computer Systems15-213, fall 200917th Lecture, Oct. 26thInstructors: Majd Sakr and Khaled HarrasCarnegie MellonLast Time: Virtual MemoryEach process gets its own private memory spaceSolves the previous problemsPhysical memoryVirtual memoryVirtual memoryProcess 1Process nmappingCarnegie MellonA System Using Virtual AddressingUsed in all modern desktops, laptops, workstationsOne of the great ideas in computer scienceMMU checks the cache0:1:M-1:Main memoryMMU2:3:4:5:6:7:Physical address(PA)Data word8:...CPUVirtual address(VA)CPU ChipCarnegie MellonLast Time: Address TranslationVirtual page number (VPN) Virtual page offset (VPO)Physical page number (PPN) Physical page offset (PPO)Virtual addressPhysical addressValid Physical page number (PPN)Page table base register(PTBR)Page table Page table address for processValid bit = 0:page not in memory(page fault)Carnegie MellonTodayVirtual memory (VM)Address translationAllocationMulti-level page tablesLinux VM systemCarnegie MellonAddress Translation: Page Hit1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory4) MMU sends physical address to cache/memory5) Cache/memory sends data word to processorMMUCache/MemoryPADataCPUVACPU ChipPTEAPTE12345Carnegie MellonAddress Translation: Page Fault1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory4) Valid bit is zero, so MMU triggers page fault exception5) Handler identifies victim (and, if dirty, pages it out to disk)6) Handler pages in new page and updates PTE in memory7) Handler returns to original process, restarting faulting instructionMMUCache/MemoryCPUVACPU ChipPTEAPTE12345DiskPage fault handlerVictim pageNew pageException67Carnegie MellonSpeeding up Translation with a TLBPage table entries (PTEs) are cached in L1 like any other memory wordPTEs may be evicted by other data referencesPTE hit still requires a 1-cycle delaySolution: Translation Lookaside Buffer (TLB)Small hardware cache in MMUMaps virtual page numbers to physical page numbersContains complete page table entries for small number of pagesCarnegie MellonTLB HitMMUCache/MemoryPADataCPUVACPU ChipPTE1245A TLB hit eliminates a memory accessTLBVPN3Carnegie MellonTLB MissMMUCache/MemoryPADataCPUVACPU ChipPTE1256TLBVPN4PTEA3A TLB miss incurs an add’l memory access (the PTE)Fortunately, TLB misses are rareCarnegie MellonSimple Memory System ExampleAddressing14-bit virtual addresses12-bit physical addressPage size = 64 bytes13 12 11 10 9 8 7 6 5 4 3 2 1 011 10 9 8 7 6 5 4 3 2 1 0VPOPPOPPNVPNVirtual Page NumberVirtual Page OffsetPhysical Page NumberPhysical Page OffsetCarnegie MellonSimple Memory System Page TableOnly show first 16 entries (out of 256)10D0F1110E12D0D0–0C0–0B1090A1170911308ValidPPNVPN0–070–06116050–0410203133020–0112800ValidPPNVPNCarnegie MellonSimple Memory System TLB16 entries4-way associative13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT0–021340A10D030–0730–030–060–080–0220–0A0–040–0212D031102070–0010D090–030ValidPPNTagValidPPNTagValidPPNTagValidPPNTagSetCarnegie MellonSimple Memory System Cache16 lines, 4-byte block sizePhysically addressedDirect mapped11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT03DFC2111167––––03161DF0723610D5098F6D431324––––03630804020011B2––––0151112311991190B3B2B1B0ValidTagIdx––––014FD31B7783113E15349604116D––––012C––––00BB3BDA159312DA––––02D98951003A1248B3B2B1B0ValidTagIdxCarnegie MellonAddress Translation Example #1Virtual Address: 0x03D4VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____Physical AddressCO ___ CI___ CT ____ Hit? __ Byte: ____13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT001010111100000x0F 3 0x03 Y N 0x0D0001010 110100 0x5 0x0D Y 0x36Carnegie MellonAddress Translation Example #2Virtual Address: 0x0B8FVPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____Physical AddressCO ___ CI___ CT ____ Hit? __ Byte: ____13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT111100011101000x2E 2 0x0B N Y TBDCarnegie MellonAddress Translation Example #3Virtual Address: 0x0020VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____Physical AddressCO___ CI___ CT ____ Hit? __ Byte: ____13 12 11 10 9 8 7 6 5 4 3 2 1 0VPOVPNTLBITLBT11 10 9 8 7 6 5 4 3 2 1 0PPOPPNCOCICT000001000000000x00 0 0x00 N N 0x280000000 001110 0x8 0x28 N MemCarnegie MellonSummaryProgrammer’s view of virtual memoryEach process has its own private linear address spaceCannot be corrupted by other processesSystem view of virtual memoryUses memory efficiently by caching virtual memory pagesEfficient only because of localitySimplifies memory management and programmingSimplifies protection by providing a convenient
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