Pentium III / Linux Memory SystemApril 4, 2000Topics• P-III address translation• Linux memory management• Linux page fault handling• memory mapping15-213class21.pptCS 213 S’00– 2 –class21.pptPentium III Memory Systembus interface unitDRAMexternal system bus (e.g. PCI)instructionfetch unitL1i-cacheL2cachecache busL1d-cacheinstTLBdataTLBprocessor package• 32 bit address space• 4 KB pagesize• L1, L2, and TLBs• 4-way set associative• inst TLB• 32 entries• 8 sets• data TLB• 64 entries• 16 sets• L1 i-cache and d-cache• 16 KB• 32 B linesize• 128 sets• L2 cache• unified• 128 KB -- 2 MBCS 213 S’00– 3 –class21.pptReview of AbbreviationsSymbols:• Components of the virtual address (VA)–TLBI: TLB index–TLBT: TLB tag–VPO: virtual page offset –VPN: virtual page number • Components of the physical address (PA)–PPO: physical page offset (same as VPO)–PPN: physical page number–CO: byte offset within cache line–CI: cache index–CT: cache tagCS 213 S’00– 4 –class21.pptOverview of P-III Address TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 andDRAML1 (128 sets, 4 lines/set)L1hitL1missCS 213 S’00– 5 –class21.pptPentium III 2-level Page Table StructurePage directory • 1024 4-byte page directory entries (PDEs) that point to page tables• one page directory per process.• page directory must be in memory when its process is running• always pointed to by PDBRPage tables:• 1024 4-byte page table entries (PTEs) that point to pages.• page tables can be paged in and out.page directory...1024 page tables1024PTEs1024PTEs1024PTEs...1024PDEsCS 213 S’00– 6 –class21.pptPentium III Page Directory Entry (PDE)Page table physical base addr Avail G PS A CD WT U/S R/W P=1Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)PS: page size 4K (0) or 4M (1)A: accessed (set by MMU on reads and writes, cleared by software)CD: cache disabled (1) or enabled (0)WT: write-through or write-back cache policy for this page tableU/S: user or supervisor mode accessR/W: read-only or read-write accessP: page table is present in memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page table location in secondary storage) P=031 01CS 213 S’00– 7 –class21.pptPentium III Page Table Entry (PTE)Page physical base address Avail G 0 D A CD WT U/S R/W P=1Page base address: 20 most significant bits of physical page address(forces pages to be 4 KB aligned)Avail: available for system programmersG: global page (don’t evict from TLB on task switch)D: dirty (set by MMU on writes)A: accessed (set by MMU on reads and writes) CD: cache disabled or enabledWT: write-through or write-back cache policy for this pageU/S: user/supervisorR/W: read/writeP: page is present in physical memory (1) or not (0)31 12 11 9 8 7 6 5 4 3 2 1 0Available for OS (page location in secondary storage) P=031 01CS 213 S’00– 8 –class21.pptHow Pentium III Page Tables Map VirtualAddresses to Physical OnesPDEPDBRphysical addressof page table base(if P=1)physical addressof page base(if P=1)physical addressof page directoryword offset into page directoryword offset into page tablepage directory page tableVPN110VPO10 12VPN2Virtual addressPTEPPN PPO2012Physical addressword offset into physical and virtualpageCS 213 S’00– 9 –class21.pptPentium III TLB translationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 andDRAML1 (128 sets, 4 lines/set)L1hitL1missCS 213 S’00– 10 –class21.pptPentium III TLBTLB entry (not all documented, so this is speculative):• V: indicates a valid (1) or invalid (0) TLB entry• PD: is this entry a PDE (1) or a PTE (0)?• tag: disambiguates entries cached in the same set• PDE/PTE: page directory or page table entry• Structure of the data TLB:• 16 sets, 4 entries/setPDE/PTE Tag PD V1 11632entry entry entry entryentry entry entry entryentry entry entry entryentry entry entry entry...set 0set 1set 2set 15CS 213 S’00– 11 –class21.pptTranslating with the Pentium III TLB1. Partition VPN into TLBT and TLBI.2. Is the PTE for VPN cached in set TLBI?3. Yes: then build physical address. 4. No: then read PTE (and PDE if not cached) from memory and build physical address.CPUVPN VPO20 12TLBT TLBI416virtual addressPDE PTE...TLBmissTLBhitpage table translationPPN PPO20 12physical address1234CS 213 S’00– 12 –class21.pptPentium III Page Table TranslationCPUVPN VPO20 12TLBT TLBI416virtual address (VA)...TLB (16 sets, 4 entries/set)VPN1 VPN21010PDE PTEPDBRPPN PPO20 12Page tablesTLBmissTLBhitphysicaladdress (PA)result32...CT CO20 5CI7L2 andDRAML1 (128 sets, 4 lines/set)L1hitL1missCS 213 S’00– 13 –class21.pptTranslating with the P-III Page Tables(Case 1/1) Case 1/1: page table and page present.MMU Action: • MMU build physical address and fetch data word.• OS action• noneVPNVPN1 VPN2PDEPDBRPPN PPO20 1220VPO12p=1 PTE p=1Data pagedataPage directoryPage tableMemDiskCS 213 S’00– 14 –class21.pptTranslating with the P-III Page Tables(Case 1/0)Case 1/0: page table present but page missing.MMU Action: • page fault exception• handler receives the following args:–VA that caused fault–fault caused by non-present page or page-level protection violation–read/write–user/supervisorVPNVPN1 VPN2PDEPDBR20VPO12p=1 PTEPage directoryPage tableMemDiskData pagedatap=0CS 213 S’00– 15 –class21.pptTranslating with the P-III Page Tables(Case 1/0, Cont)OS Action: • Check for a legal virtual address.• Read PTE through PDE. • Find free physical page (swapping out current page if necessary)• Read virtual page from disk and copy to virtual page • Restart faulting instruction by returning from exception handler.VPNVPN1 VPN2PDEPDBR20VPO12p=1 PTE p=1Page directoryPage tableData pagedataPPN PPO20 12MemDiskCS 213 S’00– 16 –class21.pptTranslating with the P-III Page Tables(Cases 0/1 and 0/0)Case 0/1: page table missing but page present.Case 0/0: page table and page missingNeither of these cases is possible because Linux doesn’t swap page tables.CS 213 S’00–
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