The Memory HierarchyOct 4, 2001Topics• Storage technologies and trends• Locality of reference• Caching in the memory hierarchyclass12.ppt15-213“The course that gives CMU its Zip!”CS 213 F’01– 2 –class12.pptRandom-Access Memory (RAM)Key features• RAM is packaged as a chip.• Basic storage unit is a cell (one bit per cell).• Multiple RAM chips form a memory.Static RAM (SRAM)• Each cell stores bit with a six-transistor circuit.• Retains value indefinitely, as long as it is kept powered.• Relatively insensitive to disturbances such as electrical noise.• Faster and more expensive than DRAM.Dynamic RAM (DRAM)• Each cell stores bit with a capacitor and transistor.• Value must be refreshed every 10-100 ms.• Sensitive to disturbances.• Slower and cheaper than SRAM.CS 213 F’01– 3 –class12.pptSRAM vs DRAM summaryTran. Accessper bit time Persist? Sensitive? Cost ApplicationsSRAM 6 1X Yes No 100x cache memoriesDRAM 1 10X No Yes 1X Main memories,frame buffersCS 213 F’01– 4 –class12.pptConventional DRAM organizationd x w DRAM:• dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)CS 213 F’01– 5 –class12.pptReading DRAM supercell (2,1)Step 1(a): Row access strobe (RAS) selects row 2.Step 1(b): Row 2 copied from DRAM array to row buffer.RAS = 2colsrows01 2 30123internal row buffer16 x 8 DRAM chiprow 2addrdata2/8/memorycontrollerCS 213 F’01– 6 –class12.pptReading DRAM supercell (2,1)Step 2(a): Column access strobe (CAS) selects column 1.Step 2(b): Supercell (2,1) copied from buffer to data lines,and eventually back to the CPU.internal buffersupercell (2,1)colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerCS 213 F’01– 7 –class12.pptMemory modules: supercell (i,j)031 78151623243263 39404748555664-bit doubleword at main memory address Aaddr (row = i, col = j)data64 MB memory moduleconsisting ofeight 8Mx8 DRAMsMemorycontrollerbits0-7DRAM 7DRAM 0bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword to CPU chipCS 213 F’01– 8 –class12.pptEnhanced DRAMsAll enhanced DRAMs are built around the conventionalDRAM core.• Fast page mode DRAM (FPM DRAM)–Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of[(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)].• Extended data out DRAM (EDO DRAM)–Enhanced FPM DRAM with more closely spaced CAS signals.• Synchronous DRAM (SDRAM)–Driven with rising clock edge instead of asynchronous control signals.• Double data-rate synchronous DRAM (DDR SDRAM)–Enhancement of SDRAM that uses both clock edges as control signals.• Video RAM (VRAM)–Like FPM DRAM, but output is produced by shifting row buffer–Dual ported (allows concurrent reads and writes)CS 213 F’01– 9 –class12.pptNonvolatile memoriesDRAM and SRAM are volatile memories• Lose information if powered off.Nonvolatile memories retain value even if powered off.• Generic name is read-only memory (ROM).• Misleading because some ROMs can be read and modified.Types of ROMs• Programmable ROM (PROM)• Eraseable programmable ROM (EPROM)• Electrically eraseable PROM (EEPROM)• Flash memoryFirmware• Program stored in a ROM–Boot time code, BIOS (basic input/ouput system)–graphics cards, disk controllers.CS 213 F’01– 10 –class12.pptBus structure connecting CPU and memoryA bus is a collection of parallel wires that carryaddress, data, and control signals.Buses are typically shared by multiple devices.mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem busmemory busCS 213 F’01– 11 –class12.pptMemory read transaction (1) ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eaxCPU places address A on the memory bus.CS 213 F’01– 12 –class12.pptMemory read transaction (2)Main memory reads A from the memory bus, retreivesword x, and places it on the bus.ALUregister filebus interfacex0Axmain memory%eaxI/O bridgeLoad operation: movl A, %eaxCS 213 F’01– 13 –class12.pptMemory read transaction (3)CPU read word x from the bus and copies it intoregister %eax.xALUregister filebus interfacexmain memory0A%eaxI/O bridgeLoad operation: movl A, %eaxCS 213 F’01– 14 –class12.pptMemory write transaction (1) CPU places address A on bus. Main memory reads itand waits for the corresponding data word to arrive.yALUregister filebus interfaceAmain memory0A%eaxI/O bridgeStore operation: movl %eax, ACS 213 F’01– 15 –class12.pptMemory write transaction (2) CPU places data word y on the bus.yALUregister filebus interfaceymain memory0A%eaxI/O bridgeStore operation: movl %eax, ACS 213 F’01– 16 –class12.pptMemory write transaction (3) Main memory read data word y from the bus andstores it at address A.yALUregister filebus interfaceymain memory0A%eaxI/O bridgeStore operation: movl %eax, ACS 213 F’01– 17 –class12.pptDisk geometryDisks consist of platters, each with two surfaces.Each surface consists of concentric rings called tracks.Each track consists of sectors separated by gaps.spindlesurfacetrackstrack ksectorsgapsCS 213 F’01– 18 –class12.pptDisk geometry (muliple-platter view) Aligned tracks form a cylinder.surface 0surface 1surface 2surface 3surface 4surface 5cylinder kspindleplatter 0platter 1platter 2CS 213 F’01– 19 –class12.pptDisk capacityCapacity: maximum number of bits that can be stored.• Vendors express capacity in units of gigabytes (GB), where 1 GB =10^6.Capacity is determined by these technology factors:• Recording density (bits/in): number of bits that can be squeezed intoa 1 inch segment of a track.• Track density (tracks/in): number of tracks that can be squeezed intoa 1 inch radial segment.• Areal density (bits/in2): product of recording and track density.Modern disks partition tracks into disjoint subsetscalled recording zones• Each track in a zone has the same number of sectors, determined bythe circumference of innermost track.• Each zone has a different number of sectors/trackCS 213 F’01– 20 –class12.ppt Computing disk capacityCapacity = (# bytes/sector) x (avg. # sectors/track) x(# tracks/surface) x (# surfaces/platter) x (# platters/disk)Example:• 512 bytes/sector• 300 sectors/track (on average)• 20,000 tracks/surface• 2 surfaces/platter• 5 platters/diskCapacity = 512 x 300 x 20000 x 2 x 5 = 30,720,000,000 = 30.72
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