15 213 Memory Technology March 15 2001 Topics class17 ppt Memory Hierarchy Basics Static RAM Dynamic RAM Magnetic Disks Access Time Gap Impact of Technology Moore s Law Observation by Gordon Moore Intel founder in 1971 Transistors Chip doubles every 18 months Has expanded to include processor speed disk capacity We Owe a Lot to the Technologists Computer science has ridden the wave Things Aren t Over Yet Technology will continue to progress along current growth curves For at least 7 10 more years Difficult technical challenges in doing so Even Technologists Can t Beat Laws of Physics Quantum effects create fundamental limits as approach atomic scale Opportunities for new devices class17 ppt 2 CS 213 S 01 Impact of Moore s Law Moore s Law Performance factors of systems built with integrated circuit technology follow exponential curve E g computer speed memory capacities double every 1 5 years Implications Computers 10 years from now will run 100 X faster Problems that appear intractable today will be straightforward Must not limit future planning with today s technology Example Application Domains Speech recognition Will be routinely done with handheld devices Breaking secret codes Need to use large enough keys Virtual Reality Complex interactive environments with real time rendering class17 ppt 3 CS 213 S 01 Computer System Processor Reg Cache Memory I O bus Memory I O controller Disk class17 ppt Disk 4 I O controller I O controller Display Network CS 213 S 01 Levels in Memory Hierarchy cache CPU regs Register size speed Mbyte block size 200 B 2 ns 8B 8B C a c h e 32 B virtual memory Memory Cache Memory 32KB 4MB 4 ns 100 MB 32 B 128 MB 60 ns 1 00 MB 8 KB 8 KB disk Disk Memory 30 GB 8 ms 0 05 MB larger slower cheaper class17 ppt 5 CS 213 S 01 Dimensions 2001 devices 0 18 m 1 cm Chip size 1 cm 1 mm 0 1 mm Diameter of Human Hair 25 m 10 m 1 m 1996 devices 0 35 m 0 1 m 6 1 nm 2007 devices 0 1 m Deep UV Wavelength 0 248 m class17 ppt 10 nm 1 Silicon atom radius 1 17 X ray Wavelength 0 6 nm CS 213 S 01 Scaling to 0 1 m Semiconductor Industry Association 1992 Technology Workshop Projected future technology based on past trends 1992 1995 1998 2001 2004 2007 Feature size m 0 5 0 35 0 25 0 18 0 12 0 10 1G 4G 16G Industry is slightly ahead of projection DRAM capacity 16M 64M 256M Doubles every 1 5 years Prediction on track Chip area cm2 2 5 4 0 6 0 8 0 10 0 12 5 Way off Chips staying small class17 ppt 7 CS 213 S 01 Static RAM SRAM Fast 4 nsec access time Persistent as long as power is supplied no refresh required Expensive 100 MByte 6 transistors bit Stable High immunity to noise and environmental disturbances Technology for caches class17 ppt 8 CS 213 S 01 Anatomy of an SRAM Cell bit line b bit line b word line Stable Configurations 0 1 Terminology bit line carries data word line used for addressing 6 transistors Write Read 1 set bit lines to new data value b is set to the opposite of b 2 raise word line to high sets cell to new state may involve flipping relative to old state class17 ppt 1 9 1 set bit lines high 2 set word line high 3 see which bit line goes low CS 213 S 01 0 SRAM Cell Principle Inverter Amplifies Negative gain Slope 1 in middle Saturates at ends Inverter Pair Amplifies Positive gain Slope 1 in middle Saturates at ends 1 0 9 0 8 0 7 0 6 0 5 V1 V2 0 4 0 3 0 2 Vin 0 1 V1 0 0 V2 class17 ppt 0 2 0 4 0 6 0 8 1 Vin 10 CS 213 S 01 Bistable Element Stability Vin Require Vin V2 Stable at endpoints recover from pertubation Metastable in middle Fall out when perturbed V1 V2 1 Stable Ball on Ramp Analogy 0 9 0 8 0 7 0 6 Metastable 0 5 Vin 0 4 V2 0 3 0 2 0 1 0 0 0 2 Stable class17 ppt 0 4 0 6 0 8 1 Vin 0 11 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 CS 213 S 01 0 9 1 Example SRAM Configuration 16 x 8 b7 b7 b1 b1 b0 b0 W0 A0 A1 A2 W1 Address decoder A3 memory cells W15 sense write amps Input output lines class17 ppt sense write amps d7 d1 12 sense write amps d0 CS 213 S 01 R W Dynamic RAM DRAM Slower than SRAM access time 60 nsec Not persistent every row must be accessed every 1 ms refreshed Cheaper than SRAM 1 50 MByte 1 transistor bit Fragile electrical noise light radiation Workhorse memory technology class17 ppt 13 CS 213 S 01 Anatomy of a DRAM Cell Word Line Bit Line Access Transistor Storage Node Cnode CBL Writing Reading Word Line Bit Line Word Line V Bit Line V Cnode CBL Storage Node class17 ppt 14 CS 213 S 01 Addressing Arrays with Bits Array Size R rows R 2r C columns C 2c N R C bits of memory Addressing address Addresses are n bits where N 2n row address address C leftmost r bits of address col address address C rightmost bits of address r c row col n Example R 2 C 4 address 6 0 1 0 000 100 1 001 101 row 1 class17 ppt 15 2 010 110 3 011 111 col 2 CS 213 S 01 Example 2 Level Decode DRAM 64Kx1 RAS Row address latch 256 Rows 8 Row decoder 256x256 cell array row 256 Columns A7 A0 column sense write amps R W col Provide 16 bit address in two 8 bit chunks Column address latch column latch and decoder 8 CAS class17 ppt Dout Din 16 CS 213 S 01 DRAM Operation Row Address 50ns Set Row address on address lines strobe RAS Entire row read stored in column latches Contents of row of memory cells destroyed Column Address 10ns Set Column address on address lines strobe CAS Access selected bit READ transfer from selected column latch to Dout WRITE Set selected column latch to Din Rewrite 30ns Write back entire row class17 ppt 17 CS 213 S 01 Observations About DRAMs Timing Access time 60ns cycle time 90ns Need to rewrite row Must Refresh Periodically Perform complete memory cycle for each row Approximately once every 1ms Sqrt n cycles Handled in background by memory controller Inefficient Way to Get a Single Bit Effectively read entire row of Sqrt n bits class17 ppt 18 CS 213 S 01 Enhanced Performance DRAMs Conventional Access RAS Row Col RAS CAS RAS CAS Page Mode Row Series of columns RAS CAS CAS CAS Gives successive bits Row address latch 8 Row decoder 256x256 cell array row A7 A0 sense write amps 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