Carnegie Mellon Introduction to Computer Systems 15 213 fall 2009 4th Lecture Sep 2nd Instructors Majd Sakr and Khaled Harras Carnegie Mellon Last Time Floating Point Fractional binary numbers IEEE floating point standard Definition Example and properties Rounding addition multiplication Floating point in C Summary Carnegie Mellon Machine Programming I Basics History of Intel processors and architectures C assembly machine code Assembly Basics Registers operands move Addressing mode address computation leal Arithmetic operations Carnegie Mellon Intel x86 Processors Totally dominate computer market Evolutionary design Backwards compatible up until 8086 introduced in 1978 Added more features as time goes on Complex instruction set computer CISC Many different instructions with many different formats But only small subset encountered with Linux programs Hard to match performance of Reduced Instruction Set Computers RISC But Intel has done just that Carnegie Mellon Intel x86 Evolution Milestones Name 8086 Date 1978 Transistors 29K MHz 5 10 First 16 bit processor Basis for IBM PC DOS 1MB address space 386 1985 275K 16 33 First 32 bit processor referred to as IA32 Added flat addressing Capable of running Unix 32 bit Linux gcc uses no instructions introduced in later models Pentium 4F 2005 230M 2800 3800 First 64 bit processor Meanwhile Pentium 4s Netburst arch phased out in favor of Core line Carnegie Mellon Intel x86 Processors Overview Architectures X86 16 Processors 8086 286 X86 32 IA32 MMX 386 486 Pentium Pentium MMX SSE Pentium III SSE2 Pentium 4 SSE3 Pentium 4E X86 64 EM64t Pentium 4F SSE4 Core 2 Duo Core i7 time IA often redefined as latest Intel architecture Carnegie Mellon Intel x86 Processors contd Machine Evolution 486 Pentium Pentium MMX PentiumPro Pentium III Pentium 4 Core 2 Duo 1989 1993 1997 1995 1999 2001 2006 1 9M 3 1M 4 5M 6 5M 8 2M 42M 291M Added Features Instructions to support multimedia operations Parallel operations on 1 2 and 4 byte data both integer FP Instructions to enable more efficient conditional operations Linux GCC Evolution Very limited Carnegie Mellon More Information Intel processors Wikipedia Intel microarchitectures Carnegie Mellon New Species ia64 then IPF then Itanium Name Itanium Date 2001 Transistors 10M First shot at 64 bit architecture first called IA64 Radically new instruction set designed for high performance Can run existing IA32 programs On board x86 engine Joint project with Hewlett Packard Itanium 2 2002 221M Big performance boost Itanium 2 Dual Core 2006 1 7B Itanium has not taken off in marketplace Lack of backward compatibility no good compiler support Pentium 4 got too good Carnegie Mellon x86 Clones Advanced Micro Devices AMD Historically AMD has followed just behind Intel A little bit slower a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp and other downward trending companies Built Opteron tough competitor to Pentium 4 Developed x86 64 their own extension to 64 bits Recently Intel much quicker with dual core design Intel currently far ahead in performance em64t backwards compatible to x86 64 Carnegie Mellon Intel s 64 Bit Intel Attempted Radical Shift from IA32 to IA64 Totally different architecture Itanium Executes IA32 code only as legacy Performance disappointing AMD Stepped in with Evolutionary Solution x86 64 now called AMD64 Intel Felt Obligated to Focus on IA64 Hard to admit mistake or that AMD is better 2004 Intel Announces EM64T extension to IA32 Extended Memory 64 bit Technology Almost identical to x86 64 Meanwhile EM64t well introduced however still often not used by OS programs Carnegie Mellon Our Coverage IA32 The traditional x86 Our unix qatar cmu edu machines x86 64 EM64T The emerging standard Presentation Book has IA32 Lecture will cover IA32 Carnegie Mellon Machine Programming I Basics History of Intel processors and architectures C assembly machine code Assembly Basics Registers operands move Addressing mode address computation leal Arithmetic operations Carnegie Mellon Definitions Architecture also instruction set architecture ISA The parts of a processor design that one needs to understand to write assembly code Microarchitecture Implementation of the architecture Architecture examples instruction set specification registers Microarchitecture examples cache sizes and core frequency Example ISAs Intel x86 IA IPF Carnegie Mellon Assembly Programmer s View Memory CPU Addresses PC Registers Condition Codes Data Instructions Object Code Program Data OS Data Stack Programmer Visible State PC Program counter Address of next instruction Called EIP IA32 or RIP x86 64 Register file Heavily used program data Condition codes Store status information about most recent arithmetic operation Used for conditional branching Memory Byte addressable array Code user data some OS data Includes stack used to support procedures Carnegie Mellon Turning C into Object Code Code in files p1 c p2 c Compile with command gcc O p1 c p2 c o p Use optimizations O Put resulting binary in file p text C program p1 c p2 c Compiler gcc S text Asm program p1 s p2 s Assembler gcc or as binary Object program p1 o p2 o Linker gcc or ld binary Executable program p Static libraries a Carnegie Mellon Compiling Into Assembly C Code int sum int x int y int t x y return t Generated IA32 Assembly sum pushl ebp movl esp ebp movl 12 ebp eax addl 8 ebp eax movl ebp esp popl ebp ret Obtain with command gcc O S code c Produces file code s Some compilers use single instruction leave Carnegie Mellon Assembly Characteristics Data Types Integer data of 1 2 or 4 bytes Data values Addresses untyped pointers Floating point data of 4 8 or 10 bytes No aggregate types such as arrays or structures Just contiguously allocated bytes in memory Carnegie Mellon Assembly Characteristics Operations Perform arithmetic function on register or memory data Transfer data between memory and register Load data from memory into register Store register data into memory Transfer control Unconditional jumps to from procedures Conditional branches Carnegie Mellon Object Code Code for sum 0x401040 0x55 0x89 0xe5 0x8b 0x45 0x0c 0x03 0x45 0x08 0x89 0xec 0x5d 0xc3 sum Total of 13 bytes Each instruction 1 2 or 3 bytes Starts at address 0x401040 Assembler Translates s into o Binary encoding of each instruction Nearly complete image of executable code Missing linkages between code in different files Linker Resolves references between files Combines with static run
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