The Memory Hierarchy February 19, 2004Random-Access Memory (RAM)SRAM vs DRAM SummaryConventional DRAM OrganizationReading DRAM Supercell (2,1)Slide 6Memory ModulesEnhanced DRAMsNonvolatile MemoriesTraditional Bus Structure Connecting CPU and MemoryMemory Read Transaction (1)Memory Read Transaction (2)Memory Read Transaction (3)Memory Write Transaction (1)Memory Write Transaction (2)Memory Write Transaction (3)Memory Subsystem TrendsDisk GeometryDisk Geometry (Muliple-Platter View)Disk CapacityComputing Disk CapacityDisk Operation (Single-Platter View)Disk Operation (Multi-Platter View)Disk Access TimeDisk Access Time ExampleLogical Disk BlocksI/O BusReading a Disk Sector (1)Reading a Disk Sector (2)Reading a Disk Sector (3)Storage TrendsCPU Clock RatesThe CPU-Memory GapLocalityLocality ExampleSlide 36Slide 37Memory HierarchiesAn Example Memory HierarchyCachesCaching in a Memory HierarchyGeneral Caching ConceptsGeneral Caching ConceptsExamples of Caching in the HierarchySummaryThe Memory HierarchyFebruary 19, 2004The Memory HierarchyFebruary 19, 2004TopicsTopicsStorage technologies and trendsLocality of referenceCaching in the memory hierarchyclass12.ppt15-213“The course that gives CMU its Zip!”– 2 –15-213, S’04Random-Access Memory (RAM)Random-Access Memory (RAM)Key featuresKey featuresRAM is traditionally packaged as a chip.Basic storage unit is normally a cell (one bit per cell).Multiple RAM chips form a memory.Static RAM (Static RAM (SRAMSRAM))Each cell stores a bit with a four or six-transistor circuit.Retains value indefinitely, as long as it is kept powered.Relatively insensitive to electrical noise (EMI), radiation, etc.Faster and more expensive than DRAM.Dynamic RAM (Dynamic RAM (DRAMDRAM))Each cell stores bit with a capacitor. One transistor is used for accessValue must be refreshed every 10-100 ms.More sensitive to disturbances (EMI, radiation,…) than SRAM.Slower and cheaper than SRAM.– 3 –15-213, S’04SRAM vs DRAM SummarySRAM vs DRAM SummaryTran. Access Needs Needsper bit time refresh? EDC? Cost ApplicationsSRAM 4 or 6 1X No Maybe 100x cache memoriesDRAM 1 10X Yes Yes 1X Main memories,frame buffers– 4 –15-213, S’04Conventional DRAM OrganizationConventional DRAM Organizationd x w DRAM:d x w DRAM:dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)– 5 –15-213, S’04Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 1(a): Row access strobe (Step 1(a): Row access strobe (RASRAS) selects row 2.) selects row 2.colsrowsRAS = 201 2 3012internal row buffer16 x 8 DRAM chip3addrdata2/8/memorycontrollerStep 1(b): Row 2 copied from DRAM array to row buffer.Step 1(b): Row 2 copied from DRAM array to row buffer.– 6 –15-213, S’04Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 2(a): Column access strobe (Step 2(a): Column access strobe (CASCAS) selects column 1.) selects column 1.colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerStep 2(b): Supercell (2,1) copied from buffer to data lines, Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.and eventually back to the CPU.supercell (2,1)supercell (2,1)To CPU– 7 –15-213, S’04Memory ModulesMemory Modules: supercell (i,j)64 MB memory moduleconsisting ofeight 8Mx8 DRAMsaddr (row = i, col = j)MemorycontrollerDRAM 7DRAM 0031 78151623243263 39404748555664-bit doubleword at main memory address Abits0-7bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword031 78151623243263 39404748555664-bit doubleword at main memory address A– 8 –15-213, S’04Enhanced DRAMsEnhanced DRAMsDRAM Cores with better interface logic and faster I/O :DRAM Cores with better interface logic and faster I/O :Synchronous DRAM (SDRAM)Uses a conventional clock signal instead of asynchronous controlDouble data-rate synchronous DRAM (DDR SDRAM)Double edge clocking sends two bits per cycle per pinRamBus™ DRAM (RDRAM)Uses faster signaling over fewer wires (source directed clocking)with a Transaction oriented interface protocolObsolete Technologies :Obsolete Technologies :Fast page mode DRAM (FPM DRAM)Allowed re-use of row-addressesExtended data out DRAM (EDO DRAM)Enhanced FPM DRAM with more closely spaced CAS signals.Video RAM (VRAM)Dual ported FPM DRAM with a second, concurrent, serial interfaceExtra functionality DRAMS (CDRAM, GDRAM)Added SRAM (CDRAM) and support for graphics operations (GDRAM)– 9 –15-213, S’04Nonvolatile MemoriesNonvolatile MemoriesDRAM and SRAM are volatile memoriesDRAM and SRAM are volatile memoriesLose information if powered off.Nonvolatile memories retain value even if powered offNonvolatile memories retain value even if powered offRead-only memory (ROM): programmed during productionMagnetic RAM (MRAM): stores bit magnetically (in development)Ferro-electric RAM (FERAM): uses a ferro-electric dielectricProgrammable ROM (PROM): can be programmed onceEraseable PROM (EPROM): can be bulk erased (UV, X-Ray)Electrically eraseable PROM (EEPROM): electronic erase capabilityFlash memory: EEPROMs with partial (sector) erase capabilityUses for Nonvolatile MemoriesUses for Nonvolatile MemoriesFirmware programs stored in a ROM (BIOS, controllers for disks, network cards, graphics accelerators, security subsystems,…)Solid state disks (flash cards, memory sticks, etc.)Smart cards, embedded systems, appliancesDisk caches– 10 –15-213, S’04Traditional Bus Structure Connecting CPU and MemoryTraditional Bus Structure Connecting CPU and MemoryA A busbus is a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signals.address, data, and control signals.Buses are typically shared by multiple devices.Buses are typically shared by multiple devices.mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem bus memory bus– 11 –15-213, S’04Memory Read Transaction (1)Memory Read Transaction (1)CPU places address A on the memory bus.CPU places address A on the memory bus. ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax– 12 –15-213, S’04Memory Read Transaction (2)Memory Read Transaction (2)Main memory reads A from the memory bus, retrieves Main memory reads A from the memory
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