Page 1The Memory HierarchyFebruary 19, 2004The Memory HierarchyFebruary 19, 2004TopicsTopics Storage technologies and trends Locality of reference Caching in the memory hierarchyclass12.ppt15-213“The course that gives CMU its Zip!”– 2 –15-213, S’04Random-Access Memory (RAM)Random-Access Memory (RAM)Key featuresKey features RAM is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Multiple RAM chips form a memory.Static RAM (Static RAM (SRAMSRAM)) Each cell stores a bit with a four or six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to electrical noise (EMI), radiation, etc. Faster and more expensive than DRAM.Dynamic RAM (Dynamic RAM (DRAMDRAM)) Each cell stores bit with a capacitor. One transistor is used for access Value must be refreshed every 10-100 ms. More sensitive to disturbances (EMI, radiation,…) than SRAM. Slower and cheaper than SRAM.– 3 –15-213, S’04SRAM vs DRAM SummarySRAM vs DRAM SummaryTran. Access Needs Needsper bit time refresh? EDC? Cost ApplicationsSRAM 4 or 6 1X No Maybe 100x cache memoriesDRAM 1 10X Yes Yes 1X Main memories,frame buffers– 4 –15-213, S’04Conventional DRAM OrganizationConventional DRAM Organizationd x w DRAM:d x w DRAM: dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)Page 2– 5 –15-213, S’04Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 1(a): Row access strobe (Step 1(a): Row access strobe (RASRAS) selects row 2.) selects row 2.colsrowsRAS = 201 2 3012internal row buffer16 x 8 DRAM chip3addrdata2/8/memorycontrollerStep 1(b): Row 2 copied from DRAM array to row buffer.Step 1(b): Row 2 copied from DRAM array to row buffer.– 6 –15-213, S’04Reading DRAM Supercell (2,1)Reading DRAM Supercell (2,1)Step 2(a): Column access strobe (Step 2(a): Column access strobe (CASCAS) selects column 1.) selects column 1.colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerStep 2(b): Step 2(b): SupercellSupercell(2,1) copied from buffer to data lines, (2,1) copied from buffer to data lines, and eventually back to the CPU.and eventually back to the CPU.supercell(2,1)supercell(2,1)To CPU– 7 –15-213, S’04Memory ModulesMemory Modules: supercell (i,j)64 MB memory moduleconsisting ofeight 8Mx8 DRAMsaddr (row = i, col = j)MemorycontrollerDRAM 7DRAM 0031 78151623243263 39404748555664-bit doubleword at main memory address Abits0-7bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword031 78151623243263 39404748555664-bit doubleword at main memory address A– 8 –15-213, S’04Enhanced DRAMsEnhanced DRAMsDRAM Cores with better interface logic and faster I/O :DRAM Cores with better interface logic and faster I/O : Synchronous DRAM (SDRAM)Uses a conventional clock signal instead of asynchronous control Double data-rate synchronous DRAM (DDR SDRAM)Double edge clocking sends two bits per cycle per pin RamBus™ DRAM (RDRAM)Uses faster signaling over fewer wires (source directed clocking)with a Transaction oriented interface protocolObsolete Technologies :Obsolete Technologies : Fast page mode DRAM (FPM DRAM)Allowed re-use of row-addresses Extended data out DRAM (EDO DRAM)Enhanced FPM DRAM with more closely spaced CAS signals. Video RAM (VRAM)Dual ported FPM DRAM with a second, concurrent, serial interface Extra functionality DRAMS (CDRAM, GDRAM)Added SRAM (CDRAM) and support for graphics operations (GDRAM)Page 3– 9 –15-213, S’04Nonvolatile MemoriesNonvolatile MemoriesDRAM and SRAM are volatile memoriesDRAM and SRAM are volatile memories Lose information if powered off.Nonvolatile memories retain value even if powered offNonvolatile memories retain value even if powered off Read-only memory (ROM): programmed during production Magnetic RAM (MRAM): stores bit magnetically (in development) Ferro-electric RAM (FERAM): uses a ferro-electric dielectric Programmable ROM (PROM): can be programmed once Eraseable PROM (EPROM): can be bulk erased (UV, X-Ray) Electrically eraseable PROM (EEPROM): electronic erase capability Flash memory: EEPROMs with partial (sector) erase capabilityUses for Nonvolatile MemoriesUses for Nonvolatile Memories Firmware programs stored in a ROM (BIOS, controllers for disks, network cards, graphics accelerators, security subsystems,…) Solid state disks (flash cards, memory sticks, etc.) Smart cards, embedded systems, appliances Disk caches– 10 –15-213, S’04Traditional Bus Structure Connecting CPU and MemoryTraditional Bus Structure Connecting CPU and MemoryA A busbusis a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signals.address, data, and control signals.Buses are typically shared by multiple devices.Buses are typically shared by multiple devices.mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem bus memory bus– 11 –15-213, S’04Memory Read Transaction (1)Memory Read Transaction (1)CPU places address A on the memory bus.CPU places address A on the memory bus.ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax– 12 –15-213, S’04Memory Read Transaction (2)Memory Read Transaction (2)Main memory reads A from the memory bus, retrieves Main memory reads A from the memory bus, retrieves word x, and places it on the bus.word x, and places it on the bus.ALUregister filebus interfacex0Axmain memory%eaxI/O bridgeLoad operation: movl A, %eaxPage 4– 13 –15-213, S’04Memory Read Transaction (3)Memory Read Transaction (3)CPU read word x from the bus and copies it into CPU read word x from the bus and copies it into register %register %eaxeax..xALUregister filebus interfacexmain memory0A%eaxI/O bridgeLoad operation: movl A, %eax– 14 –15-213, S’04Memory Write Transaction (1)Memory Write Transaction (1)CPU places address A on bus. Main memory reads it CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive.and waits for the corresponding data word to arrive.yALUregister filebus interfaceAmain memory0A%eaxI/O bridgeStore operation: movl %eax, A– 15 –15-213, S’04Memory Write Transaction (2)Memory Write Transaction (2)CPU places data word y on the
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