Page 1Topics• Memory Hierarchy Basics• Static RAM• Dynamic RAM• Magnetic Disks• Access Time Gapclass17.ppt15-213Memory TechnologyMarch 15, 2001CS 213 S’01– 2 –class17.pptImpact of TechnologyMoore’s Law• Observation by Gordon Moore, Intel founder, in 1971• Transistors / Chip doubles every 18 months– Has expanded to include processor speed, disk capacity, …We Owe a Lot to the Technologists• Computer science has ridden the waveThings Aren’t Over Yet• Technology will continue to progress along current growth curves• For at least 7–10 more years• Difficult technical challenges in doing soEven Technologists Can’t Beat Laws of Physics• Quantum effects create fundamental limits as approach atomic scale• Opportunities for new devicesCS 213 S’01– 3 –class17.pptImpact of Moore’s LawMoore’s Law• Performance factors of systems built with integrated circuit technology follow exponential curve• E.g., computer speed / memory capacities double every 1.5 yearsImplications• Computers 10 years from now will run 100 X faster• Problems that appear intractable today will be straightforward• Must not limit future planning with today’s technologyExample Application Domains• Speech recognition– Will be routinely done with handheld devices• Breaking secret codes– Need to use large enough keys• Virtual Reality– Complex interactive environments with real-time renderingCS 213 S’01– 4 –class17.pptComputer SystemDiskDiskMemory-I/O busProcessorCacheMemoryI/OcontrollerI/OcontrollerI/OcontrollerDisplay NetworkRegPage 2CS 213 S’01– 5 –class17.pptLevels in Memory HierarchyCPUregsCacheMemorydisksize:speed:$/Mbyte:block size:200 B2 ns8 BRegister Cache Memory Disk Memory32KB - 4MB4 ns$100/MB32 B128 MB60 ns$1.00/MB8 KB30 GB8 ms$0.05/MBlarger, slower, cheaper8 B 32 B 8 KBcache virtual memoryCS 213 S’01– 6 –class17.pptDimensions1 cm 1 mm 0.1 mm 10µm 1 µm 0.1 µm 10 nm 1 nm 1 ÅChip size(1 cm)Diameter ofHuman Hair(25 µm)1996 devices(0.35 µm)2007 devices(0.1 µm)Siliconatomradius(1.17 Å)Deep UVWavelength(0.248 µm)X-rayWavelength(0.6 nm)2001 devices(0.18 µm)CS 213 S’01– 7 –class17.pptScaling to 0.1µm• Semiconductor Industry Association, 1992 Technology Workshop– Projected future technology based on past trends19921995 1998 2001 2004 2007Feature size (µm ): 0.5 0.35 0.25 0.18 0.12 0.10– Industry is slightly ahead of projectionDRAM capacity: 16M 64M 256M 1G 4G 16G– Doubles every 1.5 years– Prediction on trackChip area (cm2): 2.5 4.0 6.0 8.0 10.0 12.5– Way off! Chips staying smallCS 213 S’01– 8 –class17.pptStatic RAM (SRAM)Fast• ~4 nsec access timePersistent • as long as power is supplied• no refresh required Expensive • ~$100/MByte• 6 transistors/bitStable• High immunity to noise and environmental disturbancesTechnology for cachesPage 3CS 213 S’01– 9 –class17.pptAnatomy of an SRAM Cell(6 transistors)bb’bit linebit lineword lineRead:1. set bit lines high2. set word line high3. see which bit line goes lowWrite:1. set bit lines to new data value•b’ is set to the opposite of b2. raise word line to “high”sets cell to new state (may involve flipping relative to old state)0 1Stable Configurations1 0Terminology:bit line: carries dataword line: used for addressingCS 213 S’01– 10 –class17.pptSRAM Cell PrincipleInverter Amplifies• Negative gain• Slope < –1 in middle• Saturates at endsInverter Pair Amplifies• Positive gain• Slope > 1 in middle• Saturates at endsVinV1V2V1V2Vin0 0.2 0.4 0.6 0.8 100.10.20.30.40.50.60.70.80.91CS 213 S’01– 11 –class17.pptBistable ElementStability• Require Vin = V2• Stable at endpoints– recover from pertubation• Metastable in middle– Fall out when perturbedBall on Ramp AnalogyVinV1V2VinV2Vin0 0.2 0.4 0.6 0.8 100.10.20.30.40.50.60.70.80.91StableMetastableStable0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1CS 213 S’01– 12 –class17.pptsense/writeampsExample SRAM Configuration (16 x 8)AddressdecoderA0A1A2A3b7’b7d7sense/writeampsb1’b1d1sense/writeampsb0’b0d0Input/output linesW0W1W15memorycellsR/WPage 4CS 213 S’01– 13 –class17.pptDynamic RAM (DRAM)Slower than SRAM • access time ~60 nsecNot persistent • every row must be accessed every ~1 ms (refreshed)Cheaper than SRAM • ~$1.50 / MByte• 1 transistor/bitFragile• electrical noise, light, radiationWorkhorse memory technologyCS 213 S’01– 14 –class17.pptAnatomy of a DRAM CellWord LineBitLine Storage NodeAccessTransistorCnodeCBLWritingWord LineBit LineReadingWord LineBit Line∆V ~ Cnode/ CBLVStorage NodeCS 213 S’01– 15 –class17.pptrowaddress =col0 1 2 30 000 001 010 0111 100 101 110 111row 1col 2Addressing Arrays with Bitsr cnArray Size• R rows, R = 2r• C columns, C = 2c• N = R * C bits of memoryAddressing• Addresses are n bits, where N = 2n• row(address) = address / C – leftmost r bits of address• col(address) = address % C – rightmost bits of addressExample• R = 2• C = 4• address = 6CS 213 S’01– 16 –class17.pptExample 2-Level Decode DRAM (64Kx1)RowaddresslatchColumnaddresslatchRow decoder256x256cell arraycolumnlatch and decoderA7-A0\8\8R/W’Dout DinCASRASrowcol256 Rows256 Columnscolumnsense/writeampsProvide 16-bit address in two 8-bit chunksPage 5CS 213 S’01– 17 –class17.pptDRAM OperationRow Address (~50ns)• Set Row address on address lines & strobe RAS• Entire row read & stored in column latches• Contents of row of memory cells destroyedColumn Address (~10ns)• Set Column address on address lines & strobe CAS• Access selected bit– READ: transfer from selected column latch to Dout– WRITE: Set selected column latch to DinRewrite (~30ns)• Write back entire rowCS 213 S’01– 18 –class17.pptObservations About DRAMsTiming• Access time (= 60ns) < cycle time (= 90ns)• Need to rewrite rowMust Refresh Periodically• Perform complete memory cycle for each row• Approximately once every 1ms• Sqrt(n) cycles• Handled in background by memory controllerInefficient Way to Get a Single Bit• Effectively read entire row of Sqrt(n) bitsCS 213 S’01– 19 –class17.pptEnhanced Performance DRAMsRowaddresslatchColumnaddresslatchRow decoder256x256cell arraysense/writeampscolumnlatch and decoderA7-A0\8\8R/W’CASRASrowcolEntire row buffered hererow access time col access time cycle time page mode cycle time50ns 10ns 90ns 25nsConventional Access• Row + Col• RAS CAS RAS CAS ...Page Mode• Row +
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