The Memory HierarchyFeb. 14, 2008TopicsTopicsStorage technologies and trendsLocality of referenceCaching in the memory hierarchyclass10.ppt15-213“The course that gives CMU its Zip!”215-213, S’08AnnouncementsRecitation room changesRecitation room changesC (Nate) Doherty 1211G (Pratyusa) Porter A22H (Ally) Porter A19Exam date changeExam date changeNOT Thursday, 2/21CHANGED TO Tuesday, 2/26: 7:00 p.m. - 8:30 p.m.UC McConomy XOR Wean 7500 (expect e-mail)Calculator policyCalculator policyCalculators will not be needed on the exam; hence forbidden.Collaboration reminderCollaboration reminderWriting code together counts as “sharing code” - forbiddenTalking through a problem can include pictures (not code)315-213, S’08Opinion PollPlan APlan A2/14 Thu Memory Hierarchy (DAE)2/19 Tue Opt II (REB)2/21 Thu No class? [Bill Gates]2/26 Tue Cache Memories (DAE) [Evening Exam]2/28 Thu Linking (DAE) Back to original schedulePlan BPlan B2/14 Thu Memory Hierarchy (DAE)2/19 Tue Opt II (REB)2/21 Thu Cache Memories (DAE) [Bill Gates]2/26 Tue No class? [Evening Exam]2/28 Thu Linking (DAE) Back to original schedule415-213, S’08OutlineRAMRAMROMROMDisksDisks““Mind the gap!”Mind the gap!”LocalityLocalityMemory HierarchyMemory HierarchyCachesCaches515-213, S’08Random-Access Memory (RAM)Key featuresKey featuresRAM is traditionally packaged as a chip.Basic storage unit is normally a cell (one bit per cell).Multiple RAM chips form a memory.Static RAM (Static RAM (SRAMSRAM))Each cell stores a bit with a four or six-transistor circuit.Retains value indefinitely, as long as it is kept powered.Relatively insensitive to electrical noise (EMI), radiation, etc.Faster and more expensive than DRAM.Dynamic RAM (Dynamic RAM (DRAMDRAM))Each cell stores bit with a capacitor. One transistor is used for accessValue must be refreshed every 10-100 ms.More sensitive to disturbances (EMI, radiation,…) than SRAM.Slower and cheaper than SRAM.615-213, S’08SRAM vs DRAM SummaryTran. Access Needs Needsper bit time refresh? EDC? Cost ApplicationsSRAM 4 or 6 1X No Maybe 100x cache memoriesDRAM 1 10X Yes Yes 1X Main memories,frame buffers715-213, S’08Conventional DRAM Organizationd x w DRAM:d x w DRAM:dw total bits organized as d supercells of size w bitscolsrows01 2 30123internal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)815-213, S’08Reading DRAM Supercell (2,1)Step 1(a): Row access strobe (Step 1(a): Row access strobe (RASRAS) selects row 2.) selects row 2.colsrowsRAS = 201 2 3012internal row buffer16 x 8 DRAM chip3addrdata2/8/memorycontrollerStep 1(b): Row 2 copied from DRAM array to row buffer.915-213, S’08Reading DRAM Supercell (2,1)Step 2(a): Column access strobe (Step 2(a): Column access strobe (CASCAS) selects column 1.) selects column 1.colsrows01 2 30123internal row buffer16 x 8 DRAM chipCAS = 1addrdata2/8/memorycontrollerStep 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.supercell (2,1)supercell (2,1)To CPU1015-213, S’08Memory Modules: supercell (i,j)64 MB memory moduleconsisting ofeight 8Mx8 DRAMsaddr (row = i, col = j)MemorycontrollerDRAM 7DRAM 0031 78151623243263 39404748555664-bit doubleword at main memory address Abits0-7bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword031 78151623243263 39404748555664-bit doubleword at main memory address A1115-213, S’08Enhanced DRAMsDRAM Cores with better interface logic and faster I/O :DRAM Cores with better interface logic and faster I/O :Synchronous DRAM (SDRAM)Uses a conventional clock signal instead of asynchronous controlDouble data-rate synchronous DRAM (DDR SDRAM)Double edge clocking sends two bits per cycle per pinRamBus™ DRAM (RDRAM)Uses faster signaling over fewer wires (source directed clocking)with a Transaction oriented interface protocolObsolete Technologies :Obsolete Technologies :Fast page mode DRAM (FPM DRAM)Allowed re-use of row-addressesExtended data out DRAM (EDO DRAM)Enhanced FPM DRAM with more closely spaced CAS signals.Video RAM (VRAM)Dual ported FPM DRAM with a second, concurrent, serial interfaceExtra functionality DRAMS (CDRAM, GDRAM)Added SRAM (CDRAM) and support for graphics operations (GDRAM)1215-213, S’08Nonvolatile MemoriesDRAM and SRAM are volatile memoriesDRAM and SRAM are volatile memoriesLose information if powered off.Nonvolatile memories retain value even if powered offNonvolatile memories retain value even if powered offRead-only memory (ROM): programmed during productionMagnetic RAM (MRAM): stores bit magnetically (in development)Ferro-electric RAM (FERAM): uses a ferro-electric dielectricProgrammable ROM (PROM): can be programmed onceEraseable PROM (EPROM): can be bulk erased (UV, X-Ray)Electrically eraseable PROM (EEPROM): electronic erase capabilityFlash memory: EEPROMs with partial (sector) erase capabilityUses for Nonvolatile MemoriesUses for Nonvolatile MemoriesFirmware programs stored in a ROM (BIOS, controllers for disks, network cards, graphics accelerators, security subsystems,…)Solid state disks (flash cards, memory sticks, etc.)Smart cards, embedded systems, appliancesDisk caches1315-213, S’08Traditional Bus Structure Connecting CPU and MemoryA A busbus is a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signals.address, data, and control signals.Buses are typically shared by multiple devices.Buses are typically shared by multiple devices.mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem bus memory bus1415-213, S’08Memory Read Transaction (1)CPU places address A on the memory bus.CPU places address A on the memory bus. ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax1515-213, S’08Memory Read Transaction (2)Main memory reads A from the memory bus, retrieves Main memory reads A from the memory bus, retrieves word x, and places it on the bus.word x, and places it on the bus.ALUregister filebus interfacex0Axmain memory%eaxI/O bridgeLoad operation: movl A, %eax1615-213, S’08Memory Read Transaction (3)CPU read word x from the bus and copies it into CPU read word x from the bus and copies it into register %eax.register %eax.xALUregister filebus interfacexmain memory0A%eaxI/O bridgeLoad
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