Carnegie Mellon 1 Machine(Level,Programming,I:,Basics,15#213/18#243:*Introduc3on*to*Computer*Systems**4th*Lecture,*Sep.*2,*2010*Instructors:,,Randy*Bryant*and*Dave*O’Hallaron*Carnegie Mellon 2 Today:,Machine,Programming,I:,Basics, History,of,Intel,processors,and,architec tur e s, C,,assembly,,machine,code, Assembly,Basics:,Registers,,operands,,move, Intro,to,x86(64,Carnegie Mellon 3 Intel,x86,Processors, Totally,dominate,laptop/desktop/server,market, EvoluJonary,design, Backwards*compa3ble*up*un3l*8086,*introduced*in*1978* Added*more*features*as*3me*goes*on* Complex,instrucJon,set,computer,(CISC), Many*different*instruc3ons*with*many*different*formats* But,*only*small*subset*encountered*with*Linux*programs* Hard*to*match*performance*of*Reduced*Instruc3on*Set*Computers*(RISC)* But,*Intel*has*done*just*that!* In*terms*of*speed.**Less*so*for*low*power.*Carnegie Mellon 4 Intel,x86,EvoluJon:,Milestones,!Name !Date !Transistors !MHz! 8086 ,1978 ,29K ,5(10, First*16#bit*processor.**Basis*for*IBM*PC*&*DOS* 1MB*address*space* 386 ,1985 ,275K ,16(33 ,, First*32*bit*processor*,*referred*to*as*IA32* Added*“flat*addressing”* Capable*of*running*Unix* 32#bit*Linux/gcc*uses*no*instruc3ons*introduced*in*later*models* PenJum,4F ,2004 ,125M ,2800(3800, First*64#bit*processor,*referred*to*as*x86#64* Core,i7 ,2008 ,731M ,2667(3333, Our*shark*machines*Carnegie Mellon 5 Intel,x86,Processors:,Overview,X86(64,/,EM64t,X86(32/IA32,X86(16,8086,286,386,486,PenJum,PenJum,MMX,PenJum,III,PenJum,4,PenJum,4E,PenJum,4F,Core,2,Duo,Core,i7,IA:,o[en,redefined,as,latest,Intel,archite cture,Jme,Architectures, Processors,MMX!SSE!SSE2!SSE3!SSE4!Carnegie Mellon 6 Intel,x86,Processors,,contd., Machine,EvoluJon, 386 *1985 *0.3M ** Pen3um *1993 *3.1M* Pen3um/MMX *1997 *4.5M* Pen3umPro *1995 *6.5M* Pen3um*III *1999 *8.2M* Pen3um*4 *2001 *42M* Core*2*Duo *2006 *291M* Core*i7 *2008 *731M* Added,Features, Instruc3ons*to*support*mul3media*opera3ons* Parallel*opera3ons*on*1,*2,*and*4#byte*data,*both*integer*&*FP* Instruc3ons*to*enable*more*efficient*condi3onal*opera3ons* Linux/GCC,EvoluJon, Two*major*steps:*1)*support*32#bit*386.**2)*support*64#bit*x86#64*Carnegie Mellon 7 More,InformaJon, Intel,processors,(Wikipedia), Intel,microarchitectures,Carnegie Mellon 8 New,Species:,ia64,,then,IPF,,then,Itanium,…,,!Name !Date !Transistors! Itanium ,2001 ,10M, First*shot*at*64#bit*architecture:*first*called*IA64* Radically*new*instruc3on*set*designed*for*high*performance* Can*run*exis3ng*IA32*programs* On#board*“x86*engine”* Joint*project*with*Hewlef#Packard* Itanium,2 ,2002 ,221M, Big*performance*boost* Itanium,2,Dual(Core ,2006 ,1.7B, Itanium,has,not,taken,off,in,marketplace, Lack*of*backward*compa3bility,*no*good*compiler*support,*Pen3um*4*got*too*good*Carnegie Mellon 9 x86,Clones:,Advanced,Micro,Devices,(AMD), Historically, AMD*has*followed*just*behind*Intel* A*lifle*bit*slower,*a*lot*cheaper* Then, Recruited*top*circuit*designers*from*Digital*Equipment*Corp.*and*other*downward*trending*companies* Built*Opteron:*tough*compe3tor*to*Pen3um*4* Developed*x86#64,*their*own*extension*to*64*bits*Carnegie Mellon 10 Intel’s,64(Bit, Intel,Adempted,Radical,Shi[,from,IA32,to,IA64, Totally*different*architecture*(Itanium)* Executes*IA32*code*only*as*legacy* Performance*disappoin3ng* AMD,Stepped,in,with,EvoluJonary,SoluJon, x86#64*(now*called*“AMD64”)* Intel,Felt,Obligated,to,Focus,on,IA64, Hard*to*admit*mistake*or*that*AMD*is*befer* 2004:,Intel,Announces,EM64T,extension,to,IA32, Extended*Memory*64#bit*Technology* Almost*iden3cal*to*x86#64!* All,but,low(end,x86,processors,support,x86(64, But,*lots*of*code*s3ll*runs*in*32#bit*mode*Carnegie Mellon 11 Our,Coverage, IA32, The*tradi3onal*x86* x86(64/EM64T, The*emerging*standard* PresentaJon, Book*presents*IA32*in*Sec3ons*3.1—3.12* Covers*x86#64*in*3.13* We*will*cover*both*simultaneously* Some*labs*will*be*based*on*x86#64,*others*on*IA32*Carnegie Mellon 12 Today:,Machine,Programming,I:,Basics, History,of,Intel,processors,and,architec tur e s, C,,assembly,,machine,code, Assembly,Basics:,Registers,,operands,,move, Intro,to,x86(64,Carnegie Mellon 13 DefiniJons, Architecture:,(also,instrucJon,set,architecture:,ISA),The,parts,of,a,processor,de sign,that,one,needs,to,understand,to,write,assembly,code.,, Examples:**instruc3on*set*specifica3on,*registers.* Microarchitecture:,ImplementaJon,of,the,architecture., Examples:*cache*sizes*and*core*frequency.* Example,ISAs,(Intel):,x86,,IA,,IPF,Carnegie Mellon 14 CPU,Assembly,Programmer’s,View, Programmer(Visible,State, PC:*Program*counter* Address*of*next*instruc3on* Called*“EIP”*(IA32)*or*“RIP”*(x86#64)* Register*file* Heavily*used*program*data* Condi3on*codes* Store*status*informa3on*about*most*recent*arithme3c*opera3on* Used*for*condi3onal*branching*PC,Registers,Memory,Object,Code,Program,Data,OS,Data,Addresses*Data*Instruc3ons*Stack,CondiJon,Codes, Memory, Byte*addressable*array* Code,*user*data,*(some)*OS*data* Includes*stack*used*to*support*procedures*Carnegie Mellon 15 te xt!te xt!binary!binary!Compiler,(gcc -S),Assembler,(gcc,or,as),Linker,(gcc,or ld),C,program,(p1.c p2.c),Asm,program,(p1.s p2.s),Object,program,(p1.o p2.o),Executable,program,(p),StaJc,libraries,(.a),Turning,C,into,Object,Code, Code*in*files**p1.c p2.c! Compile*with*command:**gcc –O1 p1.c p2.c -o p! Use*basic*op3miza3ons*(-O1)* Put*resul3ng*binary*in*file*p,Carnegie Mellon 16 Compiling,Into,Assembly,C,Code,int sum(int x, int y) { int t = x+y; return t; } Generated,IA32,Assembly,sum: pushl %ebp movl %esp,%ebp movl 12(%ebp),%eax addl 8(%ebp),%eax popl %ebp ret Obtain,with,command,/usr/local/bin/gcc –O1 -S code.c Produces,file,code.s Some,compilers,use,instrucJon,“leave”,Carnegie Mellon 17 Assembly,CharacterisJcs:,Data,Types, “Integer”,data,of,1,,2,,or,4,bytes,
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