15 213 The course that gives CMU its Zip Virtual Memory March 18 2004 Topics class18 ppt Motivations for VM Address translation Accelerating translation with TLBs Classic Motivations for Virtual Memory Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory Each process has its own address space Only active code and data is actually in memory Allocate more memory to process as needed Provide Protection One process can t interfere with another Because they operate in different address spaces User process cannot access privileged information Different sections of address spaces have different permissions 2 15 213 S 04 Modern Motivations for VM Memory sharing and control Copy on write share physical memory among multiple processes until a process tries to write to it At that point make a copy For example this eliminates the need for vfork Shared libraries Protection debugging via Segment Drivers Solaris Sparse address space support 64bit systems Memory as a fast communication device Part of memory is shared by multiple processes Multiprocessing beyond the scope of 15 213 3 15 213 S 04 Why does VM Work It is not used 4 15 213 S 04 Motivation 1 DRAM a Cache for Disk Full address space is quite large 32 bit addresses 4 000 000 000 4 billion bytes 64 bit addresses 16 000 000 000 000 000 000 16 quintillion bytes Disk storage is 500X cheaper than DRAM storage 80 GB of DRAM 25 000 80 GB of disk 50 To access large amounts of data in a cost effective manner the bulk of the data must be stored on disk 4 MB 500 SRAM 5 1GB 300 DRAM 160 GB 100 Disk 15 213 S 04 Levels in Memory Hierarchy cache CPU CPU regs Register Size Latency Mbyte Line size 32 B 1 ns 8 16 B 8B C a c h e virtual memory 32 B Memory 4 KB Memory Cache 32 KB 4MB 2 ns 125 MB 32 64 B Memory 1024 MB 50 ns 0 20 MB 4 64 KB disk disk Disk Memory 100 GB 8 ms 0 001 MB larger slower cheaper 6 15 213 S 04 DRAM vs SRAM as a Cache DRAM vs disk is more extreme than SRAM vs DRAM Access latencies DRAM 10X slower than SRAM Disk 160 000X slower than DRAM Importance of exploiting spatial locality First byte is 160 000X slower than successive bytes on disk vs 4X improvement for page mode vs regular accesses to DRAM Bottom line Design decisions made for DRAM caches driven by enormous cost of misses SRAM 7 DRAM Disk 15 213 S 04 Impact of Properties on Design If DRAM was to be organized similar to an SRAM cache how would we set the following design parameters Line size Large since disk better at transferring large blocks Associativity High to minimize miss rate Write through or write back Write back since can t afford to perform small writes to disk What would the impact of these choices be on miss rate Extremely low 1 hit time Must match cache DRAM performance miss latency Very high 10ms tag storage overhead Low relative to block size 8 15 213 S 04 Locating an Object in a Cache SRAM Cache Tag stored with cache line Maps from cache block to memory blocks From cached to uncached form Save a few bits by only storing tag No tag for block not in cache Hardware retrieves information can quickly match against multiple tags Object Name X X Tag Data 0 D 243 1 X J 17 105 N 1 9 Cache 15 213 S 04 Locating an Object in Cache cont DRAM Cache Each allocated page of virtual memory has entry in page table Mapping from virtual pages to physical pages From uncached form to cached form Page table entry even if page not in memory Specifies disk address Only way to indicate where to find page OS retrieves information Page Table Cache Location Data Object Name D 0 0 243 X J On Disk 1 17 105 X 10 1 N 1 15 213 S 04 A System with Physical Memory Only Examples Most Cray machines early PCs nearly all embedded systems etc Memory Physical Addresses 0 1 CPU N 1 11 Addresses generated by the CPU correspond directly to bytes in physical memory 15 213 S 04 A System with Virtual Memory Examples Memory Workstations servers modern PCs etc Virtual Addresses 0 1 Page Table 0 1 Physical Addresses CPU P 1 N 1 Disk 12 Address Translation Hardware converts virtual addresses to physical addresses via OS managed lookup table page table 15 213 S 04 Page Faults like Cache Misses What if an object is on disk rather than in memory Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory current process suspends others can resume OS has full control over placement etc Before fault Virtual Addresses Page Table Physical Addresses CPU Memory Page Table Virtual Addresses Physical Addresses CPU Disk 13 After fault Memory Disk 15 213 S 04 Servicing a Page Fault Processor Signals Controller Read block of length P starting at disk address X and store starting at memory address Y Read Occurs Direct Memory Access DMA Under control of I O controller I O Controller Signals Completion 14 Interrupt processor OS resumes suspended process 1 Initiate Block Read Processor Processor Reg 3 Read Done Cache Cache Memory I O Memory I Obus bus 2 DMA Transfer I O I O controller controller Memory Memory disk Disk disk Disk 15 213 S 04 Motivation 2 Memory Management Multiple processes can reside in physical memory How do we resolve address conflicts what if two processes access something at the same address Kernel virtual memory Stack esp Memory mapped region for shared libraries Linux x86 process memory image 0 15 memory invisible to user code Runtime heap via malloc Uninitialized data bss Initialized data data Program text text forbidden the brk ptr 15 213 S 04 Solution Separate Virt Addr Spaces Virtual and physical address spaces divided into equal sized blocks Blocks are called pages both virtual and physical Each process has its own virtual address space Operating system controls how virtual pages as assigned to physical memory Virtual Address Space for Process 1 Virtual Address Space for Process 2 16 0 Address Translation 0 VP 1 VP 2 PP 2 N 1 PP 7 0 VP 1 VP 2 N 1 Physical Address Space DRAM e g read only library code PP 10 M 1 15 213 S 04 Contrast Macintosh Memory Model MAC OS 1 9 Does not use traditional virtual memory P1 Pointer Table Process P1 Shared Address Space A B Handles Process P2 P2 Pointer Table C D E All program objects accessed through handles Indirect reference through pointer table Objects stored in shared global address space 17 15 213 S 04 Macintosh Memory
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