15 213 The course that gives CMU its Zip Main Memory and Caches Sept 23 2008 Topics lecture 09 ppt DRAM as main memory Locality of reference Caches Announcements Exam Thursday two days from now In class See exams page on class website for info and old exams Calculator policy Calculators will not be needed on the exam hence forbidden Collaboration reminder Writing code together counts as sharing code forbidden 2 Talking through a problem can include pictures not code 15 213 F 08 Byte Oriented Memory Organization 0 00 F FF Programs Refer to Virtual Memory Addresses Conceptually very large array of bytes Actually implemented with hierarchy of different memory types System provides address space private to particular process Program being executed Program can clobber its own data but not that of others Compiler Run Time System Control Allocation 3 Where different program objects should be stored All allocation within single virtual address space From class02 ppt 15 213 F 08 Simple Addressing Modes Normal R Mem Reg R Register R specifies memory address movl ecx eax Displacement D R Mem Reg R D Register R specifies start of memory region Constant displacement D specifies offset movl 8 ebp edx 4 From class04 ppt 15 213 F 08 Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address data and control signals Buses are typically shared by multiple devices CPU register file ALU memory bus bus interface 5 main memory 15 213 F 08 Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address data and control signals Buses are typically shared by multiple devices CPU register file ALU memory bus bus interface 6 main memory 15 213 F 08 Memory Read Transaction 1 Step 1 CPU places address A on the memory bus with signal indicating read CPU register file eax Load operation movl A eax ALU A bus interface 7 main memory 0 x A 15 213 F 08 Memory Read Transaction 2 Steps 2 4 Main memory reads A from the memory bus retrieves word x and places it on the bus CPU register file eax Load operation movl A eax ALU x bus interface 8 main memory 0 x A 15 213 F 08 Memory Read Transaction 3 Step 5 CPU reads word x from the bus and copies it into register eax CPU register file eax x x Load operation movl A eax ALU main memory 0 bus interface 9 x A 15 213 F 08 Memory Write Transaction 1 Step 1 CPU places address A on the memory bus with signal indicating write CPU register file eax y Store operation movl eax A ALU A bus interface 10 main memory 0 A 15 213 F 08 Memory Write Transaction 2 Step 2 CPU places data word y on the memory bus CPU register file eax y Store operation movl eax A ALU y bus interface 11 main memory 0 A 15 213 F 08 Memory Write Transaction 3 Steps 3 4 Main memory reads data word y from the bus and stores it at address A CPU register file eax y Store operation movl eax A ALU main memory 0 bus interface 12 y A 15 213 F 08 Random Access Memory RAM Key features RAM is traditionally packaged as a chip Basic storage unit is normally a cell one bit per cell Multiple RAM chips form a memory Dynamic RAM DRAM 13 Common technology for main memory Organized in two dimensions rows and columns To access select row then select column Consequence 2nd row access faster than different column row Some technical details Each cell stores bit with a capacitor One transistor is used for access Value must be refreshed every 10 100 ms 15 213 F 08 Conventional DRAM Organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 0 addr to CPU 2 3 0 2 bits rows memory controller 1 cols 1 2 8 bits 3 data 14 internal row buffer 15 213 F 08 Conventional DRAM Organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 2 bits addr to CPU rows memory controller 8 bits 0 1 0 0 1 2 3 cols 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data 15 internal row buffer 15 213 F 08 Conventional DRAM Organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 0 addr to CPU 2 3 0 2 bits rows memory controller 1 cols 1 2 8 bits 3 data 16 internal row buffer 15 213 F 08 Conventional DRAM Organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 0 addr to CPU 2 3 0 2 bits rows memory controller 1 cols 1 2 8 bits supercell 9 2 1 3 data 17 internal row buffer 15 213 F 08 Reading DRAM Supercell 9 2 1 Step 1 a Row access strobe RAS selects row 2 Step 1 b Row 2 copied from DRAM array to row buffer 16 x 8 DRAM chip 0 RAS 2 2 2 3 0 addr rows memory controller 1 cols 1 2 8 3 data 18 internal row buffer 15 213 F 08 Reading DRAM Supercell 9 2 1 Step 2 a Column access strobe CAS selects column 1 Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to the CPU 16 x 8 DRAM chip 0 CAS 1 2 rows memory controller supercell 2 1 2 3 0 addr To CPU 1 cols 1 2 8 3 data 19 supercell 2 1 internal row buffer 15 213 F 08 Multi chip Memory Modules addr row i col j supercell i j DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAM chips DRAM 7 bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 bits 0 7 0 64 bit doubleword at main memory address A Memory controller 64 bit doubleword 20 15 213 F 08 Memory access is slow Obervation memory access is slower than CPU cycles A DRAM chip has an access time of 30 50ns further systems may need 3x longer or more to get the data from memory into a CPU register With sub ns cycle times 100s of cycles per memory access and the gap has been growing Can t go to memory on every load and store 21 approximately 1 3 of instructions are loads or stores 15 213 F 08 Caches to the rescue Cache A smaller faster memory that acts as a staging area for a subset of the data in a larger slower memory 22 15 213 F 08 General cache mechanics Cache 48 9 …
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