15213 Caches March 16 2000 Topics Memory Hierarchy Locality of Reference Cache Design Direct Mapped Associative class18 ppt Computer System Processor Processor interrupt Cache Cache Memory I O Memory I Obus bus Memory Memory I O I O controller controller disk Disk class18 ppt disk Disk 2 I O I O controller controller I O I O controller controller Display Display Network Network CS 213 S 00 Levels in Memory Hierarchy cache CPU CPU regs regs Register size speed Mbyte line size 200 B 2 ns 8B 8B C a c h e 32 B Cache 32KB 4MB 4 ns 100 MB 32 B virtual memory Memory Memory Memory 128 MB 60 ns 1 50 MB 8 KB 8 KB disk disk Disk Memory 20 GB 8 ms 0 05 MB larger slower cheaper class18 ppt 3 CS 213 S 00 Alpha 21164 Chip Photo Microprocesso r Report 9 12 94 Caches L1 data L1 instruction L2 unified TLB Branch history class18 ppt 4 CS 213 S 00 Alpha 21164 Chip Caches L3 Control Right Half L2 Caches L1 data L1 instruction L2 unified TLB Branch history L1 Data L1 I n s t r Right Half L2 class18 ppt 5 L2 Tags CS 213 S 00 Locality of Reference Principle of Locality Programs tend to reuse data and instructions near those they have used recently Temporal locality recently referenced items are likely to be referenced in the near future Spatial locality items with nearby addresses tend to be referenced close together in time Locality in Example sum 0 for i 0 i n i sum a i v sum Data Reference array elements in succession spatial Instructions Reference instructions in sequence spatial Cycle through loop repeatedly temporal class18 ppt 6 CS 213 S 00 Caching The Basic Idea Main Memory Big Slow Memory Small Fast Cache Stores words A Z in example Cache Processor Stores subset of the words 4 in example Organized in lines Multiple words To exploit spatial locality A B G H A B C Y Z Access Word must be in cache for processor to access class18 ppt 7 CS 213 S 00 Initi al A B G H Basic Idea Cont Read Read C A B D A B C D C D Cache holds 2 Load line C D lines into cache Each with 2 Cache miss words Maintaining Cache Read Z Y Z C D Word already in cache Cache hit Load line Y Z into cache Evict oldest entry Each time the processor performs a load or store bring line containing the word into the cache May need to evict existing line Subsequent loads or stores to any word in line performed within cache class18 ppt 8 CS 213 S 00 Accessing Data in Memory Between any two Hierarchy levels memory is divided into lines aka blocks Data moves between levels on demand in line sized chunks Invisible to application programmer Hardware responsible for cache operation word w lines in lineaasubset hit Access wordlines v in line b miss Access Upper level of lower level w High Level v a a a b b Low Level a class18 ppt b a 9 b a CS 213 S 00 b Design Issues for Caches Key Questions Where should a line be placed in the cache line placement How is a line found in the cache line identification Which line should be replaced on a miss line replacement What happens on a write write strategy Constraints Design must be very simple Hardware realization All decision making within nanosecond time scale Want to optimize performance for typical programs Do extensive benchmarking and simulations Many subtle engineering tradeoffs class18 ppt 10 CS 213 S 00 Simplest Design Each memory line has a unique cache location Parameters Line aka block size B 2b Number of bytes in each line Typically 2X 8X word size Number of Sets S 2 s Number of lines cache can hold Total Cache Size B S 2b s Physical Address Address used to reference main memory n bits to reference N 2n total bytes Partition into fields Offset Lower b bits indicate which byte within line Set Next s bits indicate how to locate line within cache Tag Identifies this line when in cache Direct Mapped Caches n bit Physical Address t tag class18 ppt 11 s set index b offset CS 213 S 00 Indexing into Direct Mapped Cache Use set index bits to select cache set Set 0 Tag Valid 0 1 B 1 Set 1 Tag Valid 0 1 B 1 0 1 B 1 Set S 1 t tag s Tag Valid b set index offset Physical Address class18 ppt 12 CS 213 S 00 Direct Mapped Cache Tag Matching Identifying Line Must have tag match high order bits of address Must have Valid 1 t tag 1 Selected Set s b set index Tag Valid 0 1 B 1 Lower bits of address select byte or word within cache line offset Physical Address class18 ppt 13 CS 213 S 00 t 1 s 2 x xx 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Direct Mapped Cache N 16Simulation byte addresses B 2 bytes line S 4 sets E 1 b 1 x entry set Address trace reads 0 0000 1 0001 13 1101 8 1000 0 0000 0 0000 miss 13 1101 miss v tag 1 0 data m 1 m 0 1 2 data 1 0 m 1 m 0 1 1 m 13 m 12 8 1000 miss v tag data 0 0000 miss v tag data 1 1 0 m 1 m 0 1 1 m 13 m 12 1 m 9 m 8 3 class18 ppt v tag 4 14 CS 213 S 00 Why Use Middle Bits as High Order Middle Order Index Bit 4 line Cache Indexing Bit Indexing 00 01 10 11 0000 0001 0010 0011 0100 High Order Bit Indexing 0101 Adjacent memory lines would map to same cache entry 0110 Poor use of spatial locality 0111 Middle Order Bit Indexing 1000 Consecutive memory lines map 1001 to different cache lines 1010 Can hold N byte region of address space in cache at one 1011 time 1100 1101 1110 1111 class18 ppt 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CS 213 S 00 Direct Mapped Cache Implementation DECStation 3100 31 30 29 19 18 17 16 15 14 13 5 4 3 2 1 0 tag set valid tag 16 bits byte offset data 32 bits 16 384 sets data hit class18 ppt 16 CS 213 S 00 Properties of Direct Mapped Strength Caches Minimal control hardware overhead Simple design Relatively easy to make fast Weakness Vulnerable to thrashing Two heavily used lines have same cache index Repeatedly evict one to make room for other Cache Line class18 ppt 17 CS 213 S 00 Vector Product Example dot prod float x 1024 y 1024 float float sum 0 0 int i for i 0 i 1024 i sum x i y i return sum Machine DECStation 5000 MIPS Processor …
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