Print First Name Last Name Student Number University of Toronto Faculty of Applied Science and Engineering Test I February 2005 Wallberg 119 ECE532S Digital Hardware Examiner Paul Chow 1 There are 4 questions and 7 pages Do all questions The total number of marks is 45 The duration of the test is 50 minutes 2 ALL WORK IS TO BE DONE ON THESE SHEETS Use the back of the pages if you need more space Be sure to indicate clearly if your work continues elsewhere 3 No calculators or other computing devices allowed 4 Closed book No aids permitted 1 10 2 10 3 15 4 10 Total 45 Page 1 of 7 1 Starting with some short answer questions 2 marks a What was the motivation for developing the JTAG standard and what are some uses for it now 2 marks b Why do you need to turn off optimization when using gdb 2 marks c What does the mhs file do in the EDK environment 2 marks d How do you figure out the amount of memory needed for your C program 2 marks e What is technology mapping in the context of HDL based design Page 2 of 7 10 marks 2 Using a figure describe how a basic MicroBlaze system is implemented For each of the following components or functions you must show where in FPGA on board in PC etc and how they are implemented FPGA logic external chip etc Also show how all the pieces are connected MicroBlaze processor UART Ethernet physical layer interface PHY instruction and data memory using on chip memory Ethernet controller instruction and data memory using off chip memory serial port RS232 interface PHY FPGA download functions XMD stub gcc Page 3 of 7 9 marks 3 a Draw the flow diagram for an FPGA design process starting from HDL input to bit stream generation Be sure to include the individual steps involved in the physical backend part of the flow which would be found in a tool such as Xilinx ISE Briefly explain what is involved in each step of the process that you show Do not forget to show the various places where verification could be done Page 4 of 7 2 mark b What is the difference between a test bench and a test case 2 mark c What is a self checking test bench and why do you want to use them 2 mark d Designing with FPGAs means that you do not need to do verification Justify or refute this statement Page 5 of 7 4 You are in the local coffee shop and you start to think about a design problem you have for your project You have a pen lots of napkins and no calculator so the best you can do is to explore architectures that look like they could work and throw out the ones that are obviously infeasible The problem you are faced with is this You have two antennae each connected to an A D converter so that you are receiving two channels of data at the constant rate of 50MHz Fortunately the data are synchronized between each channel so that you can arrange to read both channels at the same time to generate one sample The sample can be treated as the Real and Imaginary components of a complex signal Each of the components is 12 bits For each frame of 256 samples captured you need to perform an FFT on the frame while continuing to read data from the antennae The FFT cannot be started until all 256 samples are available The FFT core will read samples from the memory one sample at a time i e it is not a parallel FFT block that takes the entire 256 samples at once The computations are done using fixed point arithmetic i e the samples can be directly processed by the core After the FFT the data is passed on to other hardware for further processing so you can just assume that the output of the FFT core is a stream of data for now The amount of memory required will easily fit within the internal memory blocks of the FPGA so you can assume you do not need external memory The internal memory can easily work at 150MHz Assume it comes in chunks of 512x36 and is only single ported 2 marks a In your IP library you have a choice of FFT cores that can process the frame in 2 s 4 s 5 s and 10 s with the obvious tradeoffs in size and power Which one will likely work the best 2 marks b You can implement a MicroBlaze system with an 80 MHz OPB bus Show why you cannot just hook up the A D FFT core and memory to the bus and use the OPB bus for all data transfers Page 6 of 7 6 marks c Show a suitable system block diagram for capturing the data and processing it through the FFT core without dropping any data at the inputs Give a brief description of how your system works Page 7 of 7
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