University of TorontoECE532 Digital HardwareModule m06: Using ISEVersion for EDK 10.1.03 and ISE 10.1.03 as of January 7, 2009IntroductionISE is an integrated environment for developing your cores for the FPGA. The main GUI is Project Navigatorand a number of other tools can be used in or launched from Project Navigator, such as CoreGen, HDLBencher, and ModelSim. You will probably do the initial development and debugging of your cores usingISE before trying to connect them to a Microblaze in EDK (XPS).Note that Xilinx tools do not work reliably if paths contain spaces. Paths with spaces should be avoidedlike the plague when deciding where to install Xilinx tools, third party tools, and where to put your projectfiles.For additional information on using ISE, please refer to the Xilinx documentation. Links to the onlinedocumentation are embedded in the PDF version of this document; most of the referenced documentationis also installed locally as part of ISE.Goals• To gain a basic understanding of how to use ISE.• To develop a simple core using ISE for use on the XUPV2P.• To use CoreGen IP in this design.• To learn how to initialize memory.• To use iMPACT to download the design to the board.• To use the pushbuttons on the XUPV2P.RequirementsAccess to ISE 10.1.03PreparationThe documentation for ISE 10.1.03 can be found here and can be also viewed directly here. The tools dealtwith in this module fall into the Design Implementation category.• Take a quick look through the ISE Help documentation in the Design Implementation tools list.• Skim through the FPGA Design Flow Overview to better understand the various tools and theirinteractions.• Skim through the ISE Quick Start Tutorial to get an idea of the additional capabilities of ISE.• If you are using the XUPV2P board, read through the Using the LEDs and Switches section of theXilinx University Program Virtex-II Pro Development System Hardware Reference Manual. You willbe using the User Input dip switches and User LEDs in this lab.1University of TorontoECE532 Digital HardwareModule m06: Using ISESteps1. Open Project Navigator.2. Create a new project in a directory (without spaces!) by selecting File → New Project.... When youspecify a Project Name, a subdirectory for it will automatically appear in the Project Location box. Inthis document, we will call it learn ise. The top-level module type will be HDL. Click Next.If you are using the XUPV2P board:• The Device Family should be Virtex2P.• The Device should be XC2VP30.• The Package should be FF896.• The Speed Grade should be -7.The Synthesis Tool should be XST and the Simulator should be ModelSim-SE Verilog (unless you haveModelSim-XE installed instead). Click Next, Next, Next, and Finish.If you are unfamiliar with the Verilog HDL language, dont worry. Verilog syntax is a cross between Cand VHDL. It is beneficial to have exposure to both Verilog and VHDL as both languages are used inindustry. is a reasonable site to visit to get an idea of how to use Verilog.With the XUPV2P board:1. Create a new text document in your project directory called example memory.coe and paste thefollowing into it:memory_initialization_radix=2;memory_initialization_vector=0101,1010,0110,1001,1100,0011,1110,0001,0000,1111,1000,0100,0010,0111,1011,1101;2. Select Project → New Source. Select IP (CoreGen & Architecture Wizard). Call it example memory.Make sure the Add to Project checkbox is checked. Click Next.3. The Select IP dialog box will pop up. Expand Memories & Storage Elements → RAMs & ROMs. SelectBlock Memory Generator v2.8. Click Next. Click Finish.4. A CoreGen GUI will pop up. Leave example memory as the Component Name. Select Single Port RAMas the memory type and let CoreGen Optimize for Area in the Primitive Selection panel. Click Next.Enter a Width of 4 and a Depth of 16 for Memory Size. This will create a ROM that has 16 4-bit words.2University of TorontoECE532 Digital HardwareModule m06: Using ISELeave all other options as their default values. Click Next. In the Memory Initialization panel, check theLoad Init File checkbox. Click on Load File... and browse to and select the COE file that you created.Click Next. Click Finish. You should get the message “Successfully generated <example memory>”in the Transcript panel at the bottom of the Project Navigator window.Note that you have just initialized a very small block of memory so it did not take very long. If youwere to initialize something occupying over 50% of the on-chip block RAM, generating the ROM couldtake upward of 10 minutes.5. Select Project → New Source. Select Verilog Module. Call it example verilog. Make sure the Add toProject checkbox is checked. Click Next.6. Create input ports system clock, sw 0, sw 1, sw 2, and sw 3 and output ports led 0, led 1, led 2,and led 3. Click Next. Click Finish7. Select File → Open... and open the example memory.veo file that was automatically generated for youby CoreGen. Copy the instantiation template from this file to your newly-created example verilog.v.Connect the ports of the memory as follows: addra with {sw 3,sw 2,sw 1,sw 0}, clka with system clock,dina with 4’h0, douta with {led 3,led 2,led 1,led 0}, and wea with 1’b0.Note: In Verilog, a pair of curly braces are used to concatenate signals. So sw 3,sw 2,sw 1,sw 0 is a4-bit vector formed by concatenating the four 1-bit sw <#> signals.Note: In Verilog a simple component instationation uses the following syntax:<name\_of\_component> <instance name> (.<component\_port\_0>(<signal\_0\_in\_instantiating\_file>).<component\_port\_1>(<signal\_1\_in\_instantiating\_file>).<component\_port\_2>(<signal\_2\_in\_instantiating\_file>));8. Save your example verolog.v file. Select Project → New Source. Select Implementation Constraints File.Call it example verilog. Make sure the Add to Project checkbox is checked. Click Next. Click Finish.9. Select example verilog.ucf from the Sources panel, then double-click on User Constraints → Edit Con-straints (Text) in the Processes panel. Copy the appropriate lines from the User Constraint Files (UCF)section Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual intoyour new UCF file.10. Save and close all the open design files.11. In the Sources in Project window you will see a collapsible listing of the source file hierarchy for theproject. Depending on which source you click on, the Processes panel will change to correspond to thatsource