Interactive Video Game Group Report An ECE532 (Digital Hardware) project of 2005 Leo Hwang (990832060) Timothy Li (990964505) March 28, 2005 Table of Contents 1. Overview.....................................................................................................................3 1.1. Goals ................................................................................................................... 3 1.2. System Block Diagram....................................................................................... 3 1.3. Brief Description of IP........................................................................................ 4 1.4. Brief Description of Software............................................................................. 4 1.5. Clock Domains.................................................................................................... 4 2. Project Outcome.......................................................................................................... 6 2.1. Review of Original Plan...................................................................................... 6 2.2. Results................................................................................................................. 6 2.3. Compromises ...................................................................................................... 6 2.3.1. Skin Detection -> Flag Detection ............................................................... 6 2.3.2. Saturation of YCbCr -> RGB Conversion.................................................. 6 2.3.3. Lines in Video Output................................................................................. 7 2.4. Suggestions for the Future .................................................................................. 7 3. Description of Hardware Blocks................................................................................. 8 3.1. External Memory Controller............................................................................... 83.2. OPB GPIO .......................................................................................................... 8 3.3. Video Input (Tvin2)............................................................................................ 8 3.3.1. tvin2.v ......................................................................................................... 8 3.3.2. Video Input Testing .................................................................................... 9 3.4. Video Output (bm_mode_svga_ctrl) .................................................................. 9 3.4.1. Video Output Testing.................................................................................. 9 3.5. ZBT Bank Switcher (zbt_mux)........................................................................... 9 3.5.1. Overview..................................................................................................... 9 3.5.2. Diagram..................................................................................................... 10 3.5.3. Controlling Buffer Rotation...................................................................... 11 3.5.4. Proper Cycling Order of Ports .................................................................. 11 3.5.5. ZBT Bank Switcher Testing ..................................................................... 12 3.6. System.mhs and System.ucf ............................................................................. 12 4. Description of Software ............................................................................................ 13 4.1. Text Drawing .................................................................................................... 13 4.1.1. Text Drawing Testing ............................................................................... 13 4.2. User Flag Detection .......................................................................................... 13 4.2.1. User Flag Detection Testing ..................................................................... 13 4.3. Video Game ...................................................................................................... 14 4.3.1. Video Game Testing ................................................................................. 14 5. Description of Design Tree....................................................................................... 15 5.1. Documentation.................................................................................................. 15 5.2. NTSC_in_VGA_out_triple_buf........................................................................ 15 5.3. Reference Designs ............................................................................................ 15 5.4. Snapshots .......................................................................................................... 15 6. References................................................................................................................. 16 6.1. Module References ........................................................................................... 16 6.2. Multimedia Board Chip References.................................................................. 1631. Overview 1.1. Goals The goal of our project was to create a video game where the user interacts by making gestures into a camera. Video game elements are superimposed onto the person’s outline and then displayed on a monitor. 1.2. System Block Diagram Figure 1 - Block diagram of project (shaded blocks denotes those we created or modified) Multimedia Board Virtex-II FPGA External Memory Controller (Xilinx IP) ZBT Bank Switcher (custom) Microblaze Processor Video Game Video Output (custom) Video Input (custom) User Detection OPB GPIO (Xilinx IP) VGA Interface (DAC) NTSC Interface (ADC) ZBT RAM Bank0 ZBT RAM Bank1 ZBT RAM Bank2 Monitor Camera OPB BusText Drawing41.3. Brief Description of IP IP Name What it does Where it came from External Memory Controller Translates memory accesses on OPB bus into memory read/write commands. Xilinx IP – with minimal changes OPB GPIO A set of software addressable input/output registers that can be connected to other IP. Xilinx IP Video Input Reads video from a camera into a ZBT memory bank. Custom Video Output Writes data from a ZBT bank to the monitor. Xilinx example – modified to work in XPS ZBT Bank Switcher