University of TorontoECE532 Digital HardwareUsing External ZBT MemoryVersion 0.02a For EDK 6.2.2 November 30, 2004GoalsYou will be learning how to connect a design to external memory.BackgroundIn previous designs you have used internal memory structures instantiated within the FPGA. This memoryhas been connected to the LMB (the Local Memory Bus). The external memory on the Multimedia Boardis ZBT memory and will be connected to the system with the OPB (On-chip Peripheral Bus).External memory can be connected to an EDK system using Xilinx’s External Memory Controller (EMC)core. The EMC is an OPB peripheral that can connect up to 8 external banks into the address space of theMicroBlaze.The Base System Builder wizzard has the ability to create a design that contains a connection to asingle ZBT bank. The design provided by the Base System Builder works. However, it does not properlysynchronize the memory clock. In more complicated designs, the clock synchronization becomes very relevant.This document describes the method used to upgrade the design provided by the Base System Builder sothat the clock to the external memory is properly synchronized.Since the memory is external to the FPGA, the delays associated with signals are large and cannot bepredicted by the FPGA tools. This problem is overcome using a feedback wire built into to the MultimediaBoard’s PCB that is the correct length to provide the correct delay. Input from this feedback wire can beused to adjust the clock driving the external memory.The Multimedia board contains a total of 5 banks of ZBT memory, providing 10Mb of space. Afterlearning how to use the EMC to connect to a single bank, this document will address how to connect all 5.RequirementsModule 1: Building a Base SystemModule 2: Adding Drivers and IPPreparation• Summaries of how to connect external memories are given in the “Connecting to Memory” section ofthe documentation for the OPB External Memory Controller Core.• You might also want to look at the Xilinx DCM (Digital Clock Manager) documentation found in theVirtex II FPGA data sheet.Connecting a Single ZBT BankStep-by-step1. Create a new system with Base System Builder as you normally would. Ensure that in ZBT 512Kx32is selected with the OPB EMC option in the Configure Additional IO Interfaces screen. You may alsowish to select Generate Sample Application and Linker Script in the Software Configuration screen as theapplication includes a test of the ZBT memory.2. Open the Add/Edit Cores dialog and add two instances of dcm module. The two DCM modules will beused to create the clocking scheme shown in Figure 1. Add the following to the ports table for each ofthe DCM modules: CLKIN, CLKFB, RST, DSSEN, PSEN, CLK0, LOCKED. Set them all as internal inscope.1University of TorontoECE532 Digital HardwareUsing External ZBT MemoryCLKINCLKFBCLK0External ClockDCMOPB_ClkSynchronous Memory BankBUFG OBUFFPGASyncmem_ClkCLKINCLKFBCLK0DCMSyncmem_Clk_fbCLKFigure 1: The clocking scheme required for external ZBT memory with clock feedback (Taken from Xilinx’sOPB EMC datasheet).Connect the ports of the first DCM module to the following nets.RST dcm rstCLKIN sys clk predcmCLKFB sys clk sPSEN net gndDSSEN net gndCLK0 sys clk sLOCKED opb dcm lockedConnect the ports of the second DCM modules to the following nets.RST dcm rstCLKIN sys clk sCLKFB zbt dcm feedbackPSEN net gndDSSEN net gndCLK0 zbt dcm clkLOCKED zbt dcm locked3. Locate the system port that connects the external sys clk pin to the net sys clk s. Change the net tosys clk predcm.4. Using the Add Port button, create an output port named ZBT 512Kx32 EMC CLK FEEDBACK OUTand an input port named ZBT 512Kx32 EMC CLK FEEDBACK IN. It is not necessary to classify theports as CLK signals. Connect the two new ports to the zbt dcm clk and zbt dcm feedback nets respec-tively. Change the C CLKIN PERIOD parameter for each DCM to 37.037. The default values for theother parameters should be sufficient. The DCM will lock when the edges of its CLKFB and CLKINinputs are aligned.5. Locate the generated port ZBT 512Kx32 EMC CLK OUT. This was generated by System Builder. No-tice that it is by default connected to sys clk s. Connect it to zbt dcm clk instead.6. Edit the system.ucf file to connect the two new ports to appropriate pins. This can be accomplishedby adding the following lines.2University of TorontoECE532 Digital HardwareUsing External ZBT MemoryNet ZBT_512Kx32_EMC_CLK_FEEDBACK_IN LOC= AE15;Net ZBT_512Kx32_EMC_CLK_FEEDBACK_IN FAST;Net ZBT_512Kx32_EMC_CLK_FEEDBACK_OUT LOC= AH14;Net ZBT_512Kx32_EMC_CLK_FEEDBACK_OUT FAST;7. The DCM takes time to synchronize the clocks and lock. During this time, it is undesirable for theMicroBlaze or other components to be operating. The LOCKED signal of the DCM can be used tokeep other components a reset state until the DCM is ready. A custom core has been created thathelps accomplish this. It can be found in~pc/532/labs/User Area/lab5.Copy the clk align core into the system’s pcores directory. Restart the EDK and add the core.8. Add an instance of the clk align core to the system and add all of its ports. Connect the ports withthe internal connections that follow:external clk sys clk predcmextend dcm reset sys rst preclkaligndcm0 locked zbt dcm lockeddcm1 locked opb dcm lockedfpga reset sys rst sdcm reset dcm rst9. Locate the system port that connects the external sys rst pin to the sys rst s net. Alter it so that itconnects to the sys rst preclkalign net.10. The system is now ready to be built and downloaded. Be aware that Base System Builder connectedthe system reset signal to User Switch SW0 on the Multimedia board. It is best to download the systemwith the switch in the reset state. However, the signal must be low in order for XMD to connect tothe MicroBlaze.11. Do a quick sanity check by running XMD and doing a memory read and a memory write to theaddress space associated with the ZBT. The address space associated with the ZBT is not the sameas the address space associated with the EMC. To find the address space, check the Parameters tab ofAdd/Edit Cores and select the instance of the opb emc.12. Run the sample application for another quick test of the ZBT memory communications.Connecting Multiple ZBT banksOne solution to connect multiple external memory banks is to use multiple EMCs. However, this is asignificant waste of FPGA logic since, as mentioned earlier, an EMC is capable of controlling up to 8 externalbanks. We will now use