University of TorontoECE532 Digital HardwareModule m06: Using ISEVersion for EDK 8.2.02i and ISE 8.2.03i as of January 5, 2007IntroductionISE is an integrated environment for developing your cores for the FPGA. The main GUI is Project Navigatorand a number of other tools can be used in or launched from Project Navigator, such as CoreGen, HDLBencher, and ModelSim. You will probably do the initial development and debugging of your cores usingISE before trying to connect them to a Microblaze in EDK (XPS).Note that Xilinx tools do not work reliably if paths contain spaces. Paths with spaces should be avoidedlike the plague when deciding where to install Xilinx tools, third party tools, and where to put your projectfiles.For additional information on using ISE, please refer to the Xilinx documentation. Links to the onlinedocumentation are embedded in the PDF version of this document; most of the referenced documentationis also installed locally as part of ISE.Goals• To gain a basic understanding of how to use ISE.• To develop a simple core using ISE for use on the Xilinx Multimedia board.• To use CoreGen IP in this design.• To learn how to initialize memory.• To use iMPACT to download the design to the board.• To use the pushbuttons on the Multimedia board.RequirementsAccess to ISE 8.2.03iPreparationThe documentation for ISE 8.2i is available online and can be either viewed directly in the browser ordownloaded for offline reading. The tools delt with in this module fall into the Design Implementationcategory.• Take a quick look through the ISE Help documentation in the Design Implementation tools list.• Skim through the FPGA Design Flow Overview to better understand the various tools and theirinteractions.• Skim through the ISE Quick Start Tutorial to get an idea of the additional capabilities of ISE.• If you are using the Multimedia board, read through the section on User Input and Output in theMicroBlaze and Multimedia Development Board User Guide. You will be using the pushbuttons, UserInput dip switches, and User LEDs in this lab.• If you are using the XUPV2P board, read through the Using the LEDs and Switches section of theXilinx University Program Virtex-II Pro Development System Hardware Reference Manual. You willbe using the User Input dip switches and User LEDs in this lab.1University of TorontoECE532 Digital HardwareModule m06: Using ISESteps1. Open Project Navigator.2. Create a new project in a directory (without spaces!) by selecting File → New Project.... When youspecify a Project Name, a subdirectory for it will automatically appear in the Project Location box. Inthis document, we will call it learn ise. The top-level module type will be HDL. Click Next.If you are using the Multimedia board:• The Device Family should be Virtex2.• The Device should be XC2V2000.• The Package should be FF896.• The Speed Grade should be -4.If you are using the XUPV2P board:• The Device Family should be Virtex2P.• The Device should be XC2VP30.• The Package should be FF896.• The Speed Grade should be -7.The Synthesis Tool should be XST and the Simulator should be ModelSim-SE Verilog (unless you haveModelSim-XE installed instead). Click Next, Next, Next, and Finish.3. If you are using the Multimedia board:(a) Unzip the m06.zip file in your project directory to get the files for this module.(b) Select Project → Add Copy of Source. Select the three Verilog files and the UCF file you justunzipped and add them to the project. Leave the default options selected in the dialog that popsup.(c) The mem init.coe file was created using Microsoft Excel and the Memory Editor as described inXilinx Answer Record #11744. Copy it into your learn ise project directory. Select Project →New Source. Select IP (CoreGen & Architecture Wizard). Call it led lookup ip. Make sure theAdd to Project checkbox is checked. Click Next.(d) The Select IP dialog box will pop up. Expand Memories & Storage Elements → RAMs & ROMs.Select Single Port Block Memory v6.2. Click Next. Click Finish.(e) A CoreGen GUI will pop up. Enter led lookup ip as the Component Name. Select Read Only asthe Port Configuration. Enter a Width of 2 and a Depth of 1024 for Memory Size. This will createa ROM that has 1024 2-bit words. Click Next. Let CoreGen Optimize for Area in the PrimitiveSelection panel. Leave all other options as their default values. Click Next. Click Next. In theInitial Contents panel, check the Load Init File checkbox. Click on Load File... and browse to andselect the COE file that you copied. Click Generate. You should get the message “Successfullygenerated <led lookup ip>” in the Transcript panel at the bottom of the Project Navigator window.Note that you have just initialized a very small block of memory so it did not take very long.If you were to initialize something occupying over 50% of the on-chip block ram, generating theROM could take upward of 10 minutes.(f) In your project directory you should now have a number of generated files for led lookup ip.The MIF file is the Memory Initialization File that can be used in behavioural simulations. The Vand VHD files are for compiling at simulation time. The VEO and VHO files are the instantiationtemplates for the IP. (Naturally, you could come up with that yourself, but copying and pastingfrom the template saves typing.)2University of TorontoECE532 Digital HardwareModule m06: Using ISE(g) Next, you will create a DCM for the module. The DCM in this module is mostly for demonstrationpurposes. You would really want to use a DCM when you need phase shifting or clock scaling.The feedback circuit works to line up or phase shift clock edges, as configured in CoreGen, andproduces a “locked” signal when the DCM output has settled. You should NOT just put a clockthrough a T flip-flop to generate another clock at half the frequency. That will cause timingheadaches.Create a DCM (Digital Clock Manager) IP in CoreGen by clicking on Project → New Source. SelectIP (CoreGen & Architecture Wizard). Call it led dcm. Make sure the Add to Project checkbox ischecked. Click Next.(h) The Select IP dialog box pops up. Expand FPGA Features and Design → Clocking → Virtex-IIPro, Virtex-II, Spartan-3. Choose Single DCM v8.2i. Click Next. Click Finish. The Xilinx ClockingWizard pops up. Enter 27 MHz as the Input Clock Frequency, since this is one of the availableclock frequencies on the Multimedia board. Ensure that RST, CLK0, CLKDV, and LOCKEDare