University of TorontoECE532 Digital HardwareModule 10: Fast Simplex Link (FSL) InterfacesVersion 1.1 For EDK 6.2i 12/1/2004Goals• To learn about the Xilinx Fast Simplex Link (FSL) Interface• To become familiar with the documentation you will need to refer to whendesigning your own systems with FSLs.IntroductionThis module will differ from the more step-by-step modules, as there is a Xil-inx application that covers how to connect user IP to the Microblaze FSL bussystem. This module is more of a guide through that example.BackgroundThe FSL is a uni-directional point-to-point connection between 2 devices thatXilinx considers to be a bus. It is essentially an abstracted, glorified FIFO witha standardized interface. The implementation differs depending on if the userneeds it to be synchronous (Both devices run on the same clock) or asynchronous(the master and slave run on different clocks), on the size, and on some otherparameters that the user can specify.A single FSL can connect only 1 master device to 1 slave device. The mas-ter writes into the FSL and the slave reads from it. Since we typically want tobe able to communicate in both directions, FSLs are often used in pairs whereeach of the 2 connected devices is a master on one of the FSLs and a slave onthe other.Requirements• Access to ISE 6.2.03i, EDK 6.2.2i, and the Xilinx Multimedia developmentboard.• Modules 1-6 so that you have a good working knowledge of EDK, pcores,and ISEPreparation• Read the FSL datasheet: <EDK-installation-dir>\hw\XilinxProcessorIPLib\pcores\fslv20 v2 00 a\doc\fsl v20.pdf1University of TorontoECE532 Digital HardwareModule 10: Fast Simplex Link (FSL) Interfaces• Read the FSL Application Note (XAPP529) http://www.xilinx.com/bvdocs/appnotes/xapp529.pdf. If you are short on time, start reading at the mid-dle of page 6 where they begin to describe the FSL interface in detail.Guiding You Through XAPP529• Download the reference design for XAPP529 at www.xilinx.com/bvdocs/appnotes/xapp529 6 2.zip• Open the project and open the Add/Edit Cores dialog. Notice that, inthe Peripherals tab, EDK has included the XAPP529 core xil idct but notthe FSLs. The FSLs are considered to be buses in EDK.• Go to the Bus Connections tab. This is where you add instances of theFSL and connect the devices to the FSLs. Do not use fsl v20 v1 00 b- it only includes the synchronous SRL FIFO version of the FSL, whichcan only be exactly 32 bits wide and 16 words deep. The fsl v20 v2 00 aversion includes the SRL FIFO version, but also can be used in with otherdepths, other physical resources, and asynchronously if needed.• In this tab you can see the FSL bus interfaces for the XAPP529 core and2 pairs of FSL bus interfaces for Microblaze. You connect them to theFSLs here.• Go to the Parameters tab. Select the MicroBlaze instance in the drop-down box. The parameter C FSL LINKS dictates how many pairs of FSLconnections are available in the Bus Connections tab. In this design, it isset to 2 even though only 1 FSL link is needed. If you select one of theFSL instances, you can set its parameters. The XAPP529 design uses theolder version of the FSL so less parameters are available to customize.Important Notes• Note that you can only have 1 master and 1 slave on a single FSL.• Note that 1 FSL link is composed of 1 pair of FSLs. If the FSL linkconnects devices A and B, one of the FSLs has device A as the master andB as the slave. The other FSL has B as the master and A as the slave.• Do not write to the FSL when the Full signal is high. Doing so will causethe FSL data to be corrupted. In the asynchronous FSL, doing so willoverwrite the word in FSL S Data with the latest data word. This is nota concern when doing writes in C code, because the MicroBlaze functionstake care of checking the FSL Full and Exists
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