Audio Data Path SystemIP BlocksAudio Controller WrapperFunctional DescriptionInterface SignalsImplementationRegister NameAsynchronous FIFO WrapperFunctional DescriptionInterface SignalsImplementationFormat ConverterFunctional DescriptionInterface SignalsImplementationSynchronous FIFO WrapperFunctional DescriptionInterface SignalsImplementationTestingAC97 Controller Loopback OperationMemory-mapped FIFOAudio Data PathNetworking componentHardware SystemTimer module and Interrupt controllerExternal memory and the DCMLight Weight Internet Protocol networking libraryPorting LWIPIntegrate LWIP into EDKCommon source and header filesTarget specific source and header filesNetwork interface ImplementationConfiguration fileArchitecture specific configuration filesMain program files source and header filesNetwork functionsLWIP functionsMain ProgramTestingHardware SystemConnectivityOutcome / ResultsAccomplishmentsAudio Data Path SystemNetwork ComponentFuture WorkAC97 ControllerFormat ConverterChipScope InsertionNetworking ComponentDescription of Design TreeAudio Data Path SystemNetworking ComponentUseful ResourcesECE 532SDigital HardwareVoice Over IPGroup Project ReportGroup members: Leonard SiuWendy CheungDue date: April 12, 2004OverviewThis project is a hardware client prototype for an existing Voice over IP (VoIP) system called Vocal Village1. The block diagram of the system is shown in Figure 1.MicroBlaze /Softw areFPGAEthernetDeviceEthernetMACcontroller(Xilinx IP)Ethernetdriver(Xilinxdriver)Async.FIFO(Xilinx IP)AC97ContollerExternal MemoryController (Xilinx IP)ZBT External MemoryAC97CodecSystemTo/From VocalVillage Serveraudio inFormatconverterDigitalClockManager(DCM)Sync.FIFO(Xilinx IP)Timer(Xilinx IP)InterruptController(Xilinx IP)OPBUART(Xilinx IP)Debugmodule(Xilinx IP)Interruptdriver(Xilinxdriver)LWIP(3rd party)OPBFigure 1: System block diagram The initial goal for the project is to establish a bi-directional audio channel that communicates with the Vocal Village server through the Internet Protocol. As the project 1 http://www.vocalvillage.net/progressed, due to time constraints, the aim was modified to doing uni-directional communication, as drawn in Figure 1. The audio input comes from a microphone connected to the Xilinx board. The AC97 Codec on the board converts this analog signal to digital. The AC97 controller configures the Codec and extracts the audio data. Further processing includes bringing the data to the OPB clock domain, converting it to a format that matches with the OPB width and storing it in a FIFO that can be accessed through the OPB. The AC97 controller also has an OPB interface, since it starts its operation when it gets signalled by the MicroBlaze processor. In the audio data path system, the FIFO blocks (one asynchronous and one synchronous) are IPs available from Xilinx. The other cores were created. The networking components include an EMAC controller (Xilinx IP), which interfaces with the Ethernet device used to interface with the Vocal Village server. Xilinxalso provides a driver for this controller. Other Xilinx IP included in the system are a Timer and an Interrupt Controller, which also have Xilinx drivers. These components areused to call a function in the Light Weight Internet Protocol (LWIP) every 100ms which is required for the networking library to function properly. ZBT (Zero Bus Turnaround) external memory was used for since the combine executable and library code is greater than the allow 64kb available with on-chip BRAM. To access this memory, an External Memory Controller (EMC), which is Xilinx IP, is used. A Digital Clock Manager (DCM)block is used to synchronize the FPGA’s internal logic and clock with the external memory’s logic and clock. In addition, a 3rd party library called LWIP was used. This library provided the client networking functionalities that is not available on the LibXil Net library from Xilinx. Audio Data Path SystemThe block diagram for the audio data path system is shown in Figure 2. On one end of the data path, it takes audio input from a microphone. Through several processing stages, the data gets stored in a FIFO that’s mapped to the OPB, so that the data can be read by an OPB master such as the MicroBlaze processor.Figure 2: Audio data path block diagramSdata_InSyncBit_ClkSdata_OutFPGA Bit_Clk OPB_Clk(12.288MHz) (50MHz)Audio Controller WrapperAC97 CtrlOPB Slave AttachmentRead FIFO WrapperSync FIFOOPB Slave AttachmentMicroBlazeProcessorOPBMic inputAC97 Codec16wr_datawr_enfullAsync FIFO16 bits16rd_datard_enemptyFormat converter32wr_datawr_enfull32 bits15 entries 32 entriesIP BlocksAudio Controller WrapperFunctional DescriptionOn the Xilinx Multimedia board, audio processing is done through the National Semiconductor LM4549 audio Codec2. This Codec is compliant with the specification for PC audio, known as AC97. The Codec uses 18-bit ADC and DAC to convert betweenanalog and digital signals, and it can also mix and process the audio signals. The role of the AC97 controller is to interface with the Codec, so that input audio signals can be exchanged between the FPGA chip and the outside world. The digital controller needs to generate a SYNC signal for the Codec to define the boundaries of each frame of audio data. Each frame consists of 1 Tag Slot and 12 Data Slots. As a 2-channel Codec, it uses only 2 of the Data Slots for audio data – one for the left channel and one for the right. The AC97 controller extracts these 2 audio data samples from the serial input line (SDATA_IN), packs them to 16-bit signals and stores them in an asynchronous FIFO. The Tag Slot and 2 other Data Slots contain Codec statusinformation and data read from a register. In this implementation of the controller, this data is not used, thus it is ignored. The rest of the slots are stuffed with zero, so the controller doesn’t look at those data bits too. The Codec is configured by setting the values of its registers; the output volume, input volume and ADC sources are examples ofoptions that can be set. To write to a register, the register address and the data to be written are embedded in the serial data (SDATA_OUT) that the controller sends to the Codec. The AC97 controller wrapper also interfaces with the OPB with a slave attachment. The purpose of this is to allow the MicroBlaze processor to write to the memory-mapped START register to signal the AC97 controller to start its