Version 1.1 1/15/2004 11:28 AMAcknowledgementGoalsPreparationBackgroundSetupUniversity of Toronto ECE532 Digital Hardware LAB 2: Adding IP and Device Drivers in XPS Version 1.1 1/15/2004 11:28 AM Acknowledgement This lab is derived from a Xilinx lab given at the University of Toronto EDK workshop in November 2003. Many thanks to Xilinx for allowing us to use and modify their material. Goals • Use Xilinx tools to add to the basic MicroBlaze system that was built in Lab1. A primary goal of this lab is to understand more details about adding IP into the system without Base System Builder and using device drivers. • The General Purpose I/O (GPIO) IP core is used in this lab together with the associated device driver. The GPIO will be added to the project and used to turn on and off User LED 0 on the board. You will manipulate the state of the LED from XMD and by using a program. • Get an introduction to the use and structure of driver code. Preparation 1. The GPIO is a simple parallel I/O port that has similar functions to the PIT used on the GIZMO board. You can have from 1 to 32 input/output ports, which corresponds to the processor having a 32-bit bus. If you use fewer than 32 ports, the advantage of working in the FPGA synthesis environment is that you will only instantiate logic for the number of ports that you require. If you are on an installed system, find the overview of the OPB GPIO in the Processor IP Reference Guide. The Guide is provided in the doc directory of the EDK install (O:\Xilinx\EDK6.1i\doc) in the file proc_ip_ref_guide.pdf. Another way to find all of the documentation is via the EDK 6.1 Documentation link in the EDK 6.1 folder. In the Guide you will find a link to the data sheet. The data sheet will also be posted on the course web page. Familiarize yourself with how this block works. Note: The Processor IP Reference Guide can only be completely viewed on an installed system because it contains many links into the installed directory tree. It will be available on the course web page, but understand that many of the hyperlinks will not work. 2. In the Processor IP Reference Guide there is also a section called the Device Driver Programmer Guide. Xilinx provides device drivers so that the user may create applications quickly and easily. The Device Driver 1University of Toronto ECE532 Digital Hardware LAB 2: Adding IP and Device Drivers in XPS Programmer Guide documents many details of the device drivers and software infrastructure. You should get familiar with this section as you may eventually need to write your own drivers. In this lab you will be required to modify some code to properly use the existing drivers. 3. You will start modifying code in this lab. If you are not familiar with any source code control system, you can quickly learn one by doing “man rcsintro” on any unix system. Using such a system is highly recommended and just good practice. You will need to run the commands from a window connected to one of the ugsparcs. There is an ssh window in the Courseware folder. 4. You will need another 15MB of disk space. Limits will be adjusted once the final class list is known. You can “clean” the files created in Lab 1 via the Tools menu to save some space. Background Processor IP is an integral part of a System-On-Chip (SOC) system. Xilinx provides a variety of processor IP cores that can quickly and easily be integrated into a system using XPS. This lab builds from Lab1 and assumes that the user has completed Lab1. A basic understanding of the EDK should have been gained from Lab1. Setup 1. Copy the XPS project directory (lab 1 folder) of the previous lab and rename the copy to “lab2”. This will be the working project directory for this lab. 2. Start XPS by selecting Courseware->Xilinx 6.1i->Xilinx Embedded Development Kit 6.1->Xilinx Platform Studio from the Windows desktop. 3. Select the File menu, select Open Project, browse to the system.xmp file of lab2. Click Open to open the project. This is the project you completed in Lab 1. Adding A GPIO With User LED 0 2 4. Select the Project menu followed by the Add/Edit Cores submenu. A dialog box is displayed. Examine all the tabs to look at the various aspects of the system that you have already built. Think about how hard it would have been to do this from scratch! Having validated (tested) ready-to-use function blocks can significantly improve your design cycle.University of Toronto ECE532 Digital Hardware LAB 2: Adding IP and Device Drivers in XPS 5. From the Peripherals Tab of the dialog box, scroll to the opb_gpio IP core in the box on the right side of the dialog box. Select the opb_gpio and click Add to add it to the system that is displayed on the left side of the dialog box. 6. Set the base address of the opb_gpio to 0x00030200 to place it at the address following the peripheral with the largest high address. The base address is the 1st address that will be decoded by the peripheral on the On-chip Peripheral Bus (OPB). Set the High Address of the device to 0x000302ff to use the minimum amount of memory space as displayed for the device. The High Address determines the range of addresses starting at the Base Address and continuing thru the High Address. What do you expect the tool to be doing with this information? 7. Select the Bus Connections tab of the dialog box. The opb_gpio is displayed as the last row in the table of peripherals on the buses. The table rows show the peripheral bus interfaces in the design and the table columns show the buses to which each peripheral interface may be attached. Clicking on a table entry will allow the peripheral to be attached to the bus. The entry is either 'M' or 's' with 'M' being a master on the bus and 's' being a slave on the bus. Select the opb_gpio to be a slave on the mb_opb. 8. Select the Parameters tab of the dialog box. Select the Open PDF Doc button on the upper right corner to open the specification for the IP. Review the parameters that can be set and signals that are to be input and output based on the application. Parameters are implemented in the IP using VHDL generics. This feature of VHDL is a large advantage for IP that must fit many different applications. 9. Switch back to the Parameters tab in XPS. Select the C_GPIO_WIDTH parameter and click Add to add it to the parameters that will be changed on the left side of the dialog