OverviewGoalsBlock DiagramBrief Description of IPReference DesignProcessor CodeVideo to ramOther IPOutcomeResultsPossible Further ImprovementsDescription of the System Componentsvideo_to_ramDecision Tree ClassifierProcessorMemory mapVGA.hHistoryMenu SystemReplayInternal Communication and External PortsVideo inputInternal CommunicationVideo outputDescription of Design TreeAppendicesExperimentation with Classification SchemesPrevious design: all processing in hardwareESC532 – Final Design Report: Real-Time Note Digitizer!Konstantine N. J. Tsotsos ( )Sanae L. M. Rosen ( )Sean C. Bell ( )Team A\/\/350/\/\3!4 April 20111Contents1 Overview 41.1 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 Brief Description of IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.1 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.2 Processor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.3.3 Video to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.3.4 Other IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Outcome 82.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 Possible Further Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Description of the System Components 103.1 video to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1.1 Decision Tree Classifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.2 VGA.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2.3 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.4 Menu System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.5 Replay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3 Internal Communication and External Ports . . . . . . . . . . . . . . . . . . . . . . . 153.3.1 Video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.2 Internal Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.3 Video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Description of Design Tree 16Appendices 17A Experimentation with Classification Schemes 17B Previous design: all processing in hardware 192List of Figures1 Projector1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Block diagram of system showing internal and external connections . . . . . . . . . . 53 Overview of IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Final decision tree for system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Memory map for SDRAM, accessed by both the processor and the video to rammodule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Design of system for processing entirely in hardware . . . . . . . . . . . . . . . . . . 19List of Tables1 Status of initially proposed features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Status of initially proposed functional requirements . . . . . . . . . …
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