System Design Overview:GoalsOriginal DesignFinal DesignBlock diagramDescription of IP Blocks:OutcomeDescription of the Blocks:Custom Designed BlocksCoreGen BlocksXilinx SVGA Controller and ZBT RAM Controller BlocksTestbenches and ModelsDescription of the Design TreeInstructions to run the systemInstructions to run the Matlab and Verilog TestbenchReferencesECE 532 Digital Hardware: Final Project Group Report Photoshop Functionalities on FPGA Group: Pearl Liu (990975307) George Ng (990857355) Date: March 28, 2005Table of Contents System Design Overview:...............................................................................................1 Goals...........................................................................................................................1 Original Design ..........................................................................................................1 Final Design................................................................................................................1 Block diagram.............................................................................................................2 Description of IP Blocks:............................................................................................3 Outcome.........................................................................................................................5 Description of the Blocks: ..............................................................................................6 Custom Designed Blocks............................................................................................6 CoreGen Blocks .......................................................................................................10 Xilinx SVGA Controller and ZBT RAM Controller Blocks ................................... 10 Testbenches and Models ...........................................................................................12 Description of the Design Tree ....................................................................................13 Instructions to run the system......................................................................................16 Instructions to run the Matlab and Verilog Testbench ................................................17 References.....................................................................................................................18System Design Overview: Goals The goal of the project was to implement a real-time video capture, Photoshop digital filter processing, and display system on FPGA. The implementation platform is the Virtex-II XC2V2000 FF896 Speed Grade –4 Development Board. Original Design The original design was to use a video capture core that would continuously capture video data from a digital camera to ZBT RAM. The captured image would then be processed by a Photoshop type of digital filter implemented in HDL code. The filtered image would then be displayed on a VGA monitor using a VGA display controller. The entire process would be performed in real-time. Final Design All parts of the proposed project were implemented except for the real-time video capture component. This decision was taken to simplify our project. Instead of capturing the image in real-time, an image was loaded from a separate project into the ZBT RAM. A 32-bit (flipped row order) bitmap image file format was used. From our research we found that the pixel RGB (red, green, and blue) components in a bitmap are stored directly in consecutive bytes, where each byte represents the pixel color. To simplify the design of the memory controller, we decide to use a 32-bit bitmap file format over a 24-bit bitmap format (the 32-bit bitmap file format uses 24-bits to store the color data and pads the remaining 8-bits). This was done since the ZBT RAM reads out 32-bits at a time. In the case of 24-bit bitmaps, the RGB components of a pixel can potentially straddle a 32-bit boundary, as result; multiple reads may be needed performed to retrieve a single pixel, thus complicating the memory controller design. The way our design works is that once there is image data in the ZBT RAM, it will immediately send the data to the digital filter within the FPGA. The filtered data is then passed on to a 32 bit x 32 deep FIFO using a custom designed ZBT memory to FIFO controller. Once the FIFO becomes full, a FIFO to display controller is used to transfer the filtered data out of the FIFO and to the SVGA display controller. The SVGA controller provided by Xilinx handled the reads and writes from a ZBT video memory bank within the display block and the filtered image would be immediately displayed on the monitor. 1Block diagram Digital Photoshop Filter and Display Blocks 2Bitmap image loader Bitmap image loader is the direct implementation of lab m08. It is used to initially load image data into a ZBT RAM bank 0. No further description is provided. Lab m08 can be found at: http://www.eecg.toronto.edu/~pc/courses/edk/modules/6.3/m08.pdf Description of IP Blocks: IP Block Functionality Origin Custom Blocks displaypattern.v Top level hardware block which connects the FIFO, ZBT controllers, and custom controllers Custom design by George and Pearl mem2fifo_ctrl.v Takes image data from ZBT RAM and inputs it through the filter and into the FIFO. Custom Design by George 3fifo2disp_ctrl.v Takes image data from the FIFO and inputs it into display controller Custom Design by George gblur.v Low pass filter code that blurs an image Custom Design by Pearl emboss.v High pass filter code that embosses an image Custom Design by Pearl Xilinx Display Controller and ZBT RAM Controller ADDR_BUS_INTERFACE.v Address bus interface for ZBT RAM controller Xilinx SVGA IP BM_MODE_SVGA_CTRL.v SVGA controller Xilinx SVGA IP modified by connecting the RAM and SVGA controller to the same pixel_clock CTRL_BUS_INTERFACE.v Control bus interface for the ZBT RAM controller Xilinx SVGA IP DATA_BUS_INTERFACE.v Data bus interface for the ZBT RAM controller Xilinx SVGA IP DRIVE_DAC_DATA.v Directs data to SVGA Xilinx SVGA IP MEMORY_CTRL.v Memory controller module of ZBT RAM Xilinx SVGA IP PIPELINES.v Provides pipelines for data WRITES and a latch for the data READS in ZBT Xilinx SVGA IP SVGA_TIMING_GENERATION.v Generates timing and control signal for DAC & VGA output connector Xilinx SVGA IP ZBT_CONTROL.v ZBT RAM controller top level interface