University of TorontoECE532 Digital HardwareUsing External ZBT MemoryVersion for EDK 6.3, Feb. 14, 2005.1 GoalsYou will be learning how to connect external memory to the OPB bus controller.If you wish to use a controller that does not have the OPB bus interface you should still go through thismodule to become familiar with the clocking issues and then look at Section 7.2 BackgroundIn previous designs you have used internal memory structures instantiated within the FPGA. This memoryhas been connected to the LMB (the Local Memory Bus). The external memory on the Multimedia Boardis ZBT memory and will be connected to the system with the OPB (On-chip Peripheral Bus).External memory can be connected to an EDK system using Xilinx’s External Memory Controller (EMC)core. The EMC is an OPB peripheral that can connect up to 8 external banks into the address space of theMicroBlaze.The Base System Builder wizard has the ability to create a design that contains a connection to a singleZBT bank. The design provided by the Base System Builder works. However, it does not properly handlethe memory clocking. In more complicated designs, the clock synchronization becomes very relevant. Thisdocument describes how to modify the design provided by the Base System Builder so that the clock to theexternal memory is properly synchronized to the internal clock.For high-speed interfaces, such as the ZBT memory, it is necessary to account for delays through theFPGA and on the traces of the PCB. The Digital Clock Manager (DCM) available on the Xilinx Virtex IIFPGA can be used to account for these delays.A clock feedback wire, with delay equal to the clock lines to the five memory chips according to theMultimedia User Guide, is available to align the phase of the internal clocks to the clock arriving at thememory chips using a DCM.The Multimedia board contains a total of five banks of ZBT memory, providing 10MB of space. Afterlearning how to use the EMC to connect to a single bank, this document will address how to connect all fivebanks.3 RequirementsModule 1: Building a Base SystemModule 2: Adding Drivers and IP4 Preparation• Summaries of how to connect external memories are given in the “Connecting to Memory” section ofthe documentation for the OPB External Memory Controller Core.• You might also want to look at the Xilinx DCM (Digital Clock Manager) documentation found in theVirtex II FPGA data sheet.5 Connecting a Single ZBT Bank5.1 Step-by-step1. Create a new system with Base System Builder as you normally would. Ensure that in ZBT 512Kx32is selected with the OPB EMC option in the Configure Additional IO Interfaces screen. You may also1University of TorontoECE532 Digital HardwareUsing External ZBT Memorywish to select Generate Sample Application and Linker Script in the Software Configuration screen as theapplication includes a test of the ZBT memory.2. Open the Add/Edit Cores dialog and add two instances of dcmmodule. The two DCM modules will beused to create the clocking scheme shown in Figure 1. Add the following to the ports table for each ofthe DCM modules: CLKIN, CLKFB, RST, DSSEN, PSEN, CLK0, LOCKED. Set them all as internal inscope.CLKINCLKFBCLK0External ClockDCMOPB_ClkSynchronous Memory BankBUFG OBUFFPGASyncmem_ClkCLKINCLKFBCLK0DCMSyncmem_Clk_fbCLKFigure 1: The clocking scheme required for external ZBT memory with clock feedback (Taken from Xilinx’sOPB EMC datasheet).Connect the ports of the first DCM module to the following nets.RST dcm rstCLKIN sys clk predcmCLKFB sys clk sPSEN net gndDSSEN net gndCLK0 sys clk sLOCKED opb dcm lockedConnect the ports of the second DCM modules to the following nets.RST dcm rstCLKIN sys clk sCLKFB zbt dcm feedbackPSEN net gndDSSEN net gndCLK0 zbt dcm clkLOCKED zbt dcm locked3. Locate the system port that connects the external sys clk pin to the net sys clk s. Change the net tosys clk predcm.4. Using the Add Port button, create an output port named ZBT 512Kx32 EMC CLK FEEDBACK OUTand an input port named ZBT 512Kx32 EMC CLK FEEDBACK IN. It is not necessary to classify theports as CLK signals. Connect the two new ports to the zbt dcm clk and zbt dcm feedback nets respec-tively. Change the C CLKIN PERIOD parameter for each DCM to 37.037. The default values for the2University of TorontoECE532 Digital HardwareUsing External ZBT Memoryother parameters should be sufficient. The DCM will lock when the edges of its CLKFB and CLKINinputs are aligned.5. Locate the generated port ZBT 512Kx32 EMC CLK OUT. This was generated by System Builder. No-tice that it is by default connected to sys clk s. Connect it to zbt dcm clk instead.6. Edit the system.ucf file to connect the two new ports to appropriate pins. This can be accomplishedby adding the following lines.Net ZBT_512Kx32_EMC_CLK_FEEDBACK_IN LOC= AE15;Net ZBT_512Kx32_EMC_CLK_FEEDBACK_IN FAST;Net ZBT_512Kx32_EMC_CLK_FEEDBACK_OUT LOC= AH14;Net ZBT_512Kx32_EMC_CLK_FEEDBACK_OUT FAST;7. The DCM takes time to synchronize the clocks and lock. During this time, it is undesirable for theMicroBlaze or other components to be operating. The LOCKED signal of the DCM can be used to keepother components in a reset state until the DCM is ready. A custom core (clk align v1 00 a) hasbeen created that helps accomplish this. It can be found in the zip file for this module.Copy the clk align core into the system’s pcores directory. Restart the EDK and add thecore.8. Add an instance of the clk align core to the system and add all of its ports. Connect theports with the internal connections that follow:external clk sys clk predcmextend dcm reset sys rst preclkaligndcm0 locked zbt dcm lockeddcm1 locked opb dcm lockedfpga reset sys rst sdcm reset dcm rst9. Locate the system port that connects the external sys rst pin to the sys rst s net. Alterit so that it connects to the sys rst preclkalign net.10. The system is now ready to be built and downloaded. Be aware that Base System Builderconnected the system reset signal to User Switch SW0 on the Multimedia board. It is bestto download the system with the switch in the reset state. However, the signal must below in order for XMD to connect to the MicroBlaze.11. Do a quick sanity check by running XMD and doing a memory read and a memory write to theaddress space associated with the ZBT. The address space associated with the ZBT is notthe same as the address space associated with the EMC. To find the address space, checkthe Parameters tab of Add/Edit Cores and select the instance of the