University of TorontoECE532 Digital HardwareModule m07: Using ModelSim to Simulate Your DesignsVersion for ModelSim SE 6.2e as of January 11, 2007IntroductionModelSim is a powerful HDL simulation tool that allows you to stimulate the inputs of your modules andview both outputs and internal signals. It allows you to do both behavioural and timing simulation, however,this document will focus on behavioural simulation.In behavioural simulation, you can write models that will not necessarily synthesize. An example is abehavioural model for the ZBT RAMs used on the Xilinx Multimedia board. This code cannot be synthesized,but it is intended to give a true reflection of the behaviour of the memory chip so that you can test whetheryour memory controller is functioning properly.This module is intended as a quick intro to using ModelSim in the UofT environment. Other resourcesfor ModelSim are linked on the UofT EDK page.Source Files for ExamplesDownload and unzip the m07.zip file from the UofT EDK Tutorials page.Using the ModelSim GUIWhile there are many things you can do with ModelSim, these are the basic things you will need to getstarted.1. If you are using a Windows-based system, launch ModelSim from the Courseware directory. Otherwise,if you are logged in on the ECF Linux workstations, make sure [email protected] is inyour LM LICENSE FILE environment variable and then launch /local/packages/modeltech/bin/vsim.2. From the Modelsim GUI, change directory to your project directory, which should include your designfiles and testbench.3. Type the following command to create a ModelSim working directory called “work”. This is whereModelsim will compile your design to (GUI: menu File → New → Directory):% vlib work4. Before simulating your design, you need to compile the source files and testbench. For hierarchicaldesigns, compile the lower level design blocks before the higher level design blocks. To compile, (GUI:menu Compile → Compile) type the following commands:% vlog <design_file>.v% vcom <design_file2>.vhd% vlog <testbench>.v5. To simulate your design, type the following command:% vsim <working_directory>.<topmost_module_name>6. For example, if your working directory is “work” and your design has topmost module named “top”(GUI: menu Simulate → Simulate, select the topmost module name from the “Design” tab):% vsim work.top1University of TorontoECE532 Digital HardwareModule m07: Using ModelSim to Simulate Your Designs7. If this is a post-synthesis simulation or if any Xilinx core macros are instantiated in your Verilog sourcecode, you must compile the simulation libraries before simulating. Once the libraries are compiled,use the -L flag to reference the compiled libraries (GUI: add the library to reference in the “Libraries”tab).You can open the Wave window, the Signal window, and the Workspace window from the main GUI bygoing to the View menu.In the Workspace window, you can expand the module’s hierarchy. The signals in the Signal windowwill correspond to the level selected in the Workspace window. Expanding and selecting a level in the mainModelSim window Workspace “sim” tab has the same effect. The signals can then be dragged and droppedfrom the Signals window into the Wave window for viewing.If you are debugging, you will probably wish to use the same set of signals every time you simulate thismodule. You can save the format of the signals, radix, dividers, and labels by selecting File → Save Formatin the Wave window. This will save the format (not the simulation data) to a .do file. Sometimes you mayfind it useful to modify the .do file by hand instead of manipulating signal names from the Wave windowGUI.Once the signals are in the Wave window, you can Restart the simulation by typing “restart -force”. Youcan then run the testbench by clicking on the Run -All button on the Wave window toolbar. Alternately,you could type “run -all” at the ModelSim command prompt in the main ModelSim window to run thetestbench.As you make modifications to your HDL during debugging, you will have to re-compile it within ModelSimbefore re-simulating. Note that, for simulation purposes, re-synthesizing your HDL in the Xilinx tools willhave no impact besides helping to find syntax errors.New to ModelSim 6.2eThe optimizer, VOPT, is now run by default when you launch VSIM to simulate your designs. This has thebenefit of making your simulations run considerably faster, with the side-effect of making it impossible tomonitor internal signals by default. You can prevent VOPT from being invoked automatically by including-novopt in your VCOM, VLOG, and VSIM invokations. Alternatively, you can enable optimizatino withincreased symbol visibility for a smaller performance penalty by using the +acc flag to VOPT (similar to the-g flag for GCC). For instance, when you launch VSIM, you can use the command vsim -voptargs="+acc"to enable full debug access to your design.A Simple ExampleAs a basic example, consider the simulation of a full-adder.1. Launch the ModelSim GUI.2. Change directory in ModelSim to lab7/full adder/.3. From the ModelSim command window, type the following command to create a ModelSim workingdirectory called “work”.% vlib work4. Compile the full adder.v Verilog file.% vlog full_adder.v5. Start the simulation on the top-level entity (full adder).% vsim work.full_adder2University of TorontoECE532 Digital HardwareModule m07: Using ModelSim to Simulate Your DesignsNote that ModelSim informs you that VOPT is being run:# ** Note: (vsim-3812) Design is being optimized...6. Add the Wave and Workspace windows to the GUI.% view wave% view workspaceNote: For earlier of versions Modelsim, the workspace window was called the structure window. Hence,the above commands would have to be replaced as follows:% view wave% view structure7. Position the Wave and Worksapce windows such that they are both visible on the screen. Drag thefull adder block from the Workspace window onto the leftmost column of the Wave window. Thefollowing five signals should be added to the leftmost column of the Workspace window./full_adder/a/full_adder/b/full_adder/cin/full_adder/sum/full_adder/coutNote that the Visibility column in the Workspace window shows that the full adder block was opti-mized with +acc=<none>.8. Return to the main Modelsim GUI window. Type the following commands to “force” the inputs to setvalues.% force a 0% force b 1% force cin 19. Run the simulation