University of TorontoFaculty of Applied Science and EngineeringTest 2 – April 2004ECE532S – Digital HardwareExaminer – Paul Chow1. There are 5 questions and 10pages. Do all questions. The total number of marks is 50. The durationof the test is 50 minutes.2. ALL WORK IS TO BE DONE ON THESE SHEETS! Use the back of the pages if you need morespace. Be sure to indicate clearly if your work continues elsewhere.3. No calculators or other computing devices allowed.4. Closed book. No aids permitted.1 [10]2 [10]3 [10]4 [10]5 [10]Total [50]Print:First Name:. . . . .. . . . . . . . . . . . . . . . . . . . . . . . Last Name:. . . . . . . . . . . . . . . . . . . . . . . . . . . . .Student Number:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 1 of 101. Starting with some short answer questions:(a) Define setup and hold time for a flip flop.[2 marks](b) What happens when a flip flop goes metastable and how long will it stay in that state?[2 marks](c) What is a clock domain?[2 marks](d) Why is flip chip bonding preferred for high-speed packaging?[2 marks](e) What is jitter in the context of timing analysis?[2 marks]Page 2 of 102. Using a figure, describe how a basic MicroBlaze system is implemented. For each of the following[10 marks]components or functions you must show where (in FPGA, on board, in PC, etc.) and how they areimplemented (FPGA logic, external chip, etc.). Also show how all the pieces are connected.MicroBlaze processorUARTEthernet physical layer interface (PHY)instruction and data memory using on-chip memoryEthernet controllerinstruction and data memory using off-chip memoryserial port (RS232) physical driversFPGA download functionsXMD stubgccPage 3 of 103. Consider the circuit shown below:D Q D QCombLogic350ps4ns50MHzClockFrom the data sheets you have also gathered the following information about the flip flops:setup hold ClockToQ The clock tree has a maximum skew of, i.e., the phase of any one branch could be ahead orbehind the other by.The clock source is a 50 MHz clock, orperiod with a jitter of.(a) There is a delay ofaccounting for the combinational logic and the wire delay for the data[5 marks]travelling between the two flip flops.Being a very conservative designer, you also like to addof timing margin to all of yourcalculations.Determine whether the circuit will operate correctly (assuming that you include your own timingmargin) by checking the setup and hold times for the receiving flip flop in the above circuit.Page 4 of 10Question 3(a) continued...Page 5 of 10(b) You also know of a similar circuit in another part of your design, except that it does not have the[5 marks]combinational logic. The output of the first flip flop connects directly to the input of the secondflip flop. Assuming that the routing delay is, determine whether this circuit meets timing.Page 6 of 104. You have inherited the anti-lock braking system module for a car as the next task in your job. Therehave been numerous reports of the system not working properly. The circuit capturing the data fromthe shaft encoder to calculate the speed is shown below.16−bitBinaryCounter1616−bitReg16100 MHzLogicShaft EncoderEnable100 MHzThe shaft encoder generates 1000 pulses per revolution. The pulses are counted in the 16-bit binarycounter. The value of the counter is periodically sampled in the 100MHz domain when the Enablesignal goes high. The sampling period is frequent enough that the 16-bit counter has adequate range.(a) Why is this circuit unreliable? Give an example of how it could fail.[5 marks]Page 7 of 10Question 4 continued...(b) How would you fix this circuit? You are free to start over with a new design, except that the[5 marks]same shaft encoder is to be used and the core logic should run at 100MHz.Page 8 of 105. You have just joined a new company as the team leader of the ASIC verification group. After a numberof weeks of hiring, you are now meeting your team of young recruits who are fresh out of school.(a) What will you tell your team about the importance of simulation in the overall ASIC design[3 marks]flow?(b) Your team has just grown to add some people that will be responsible for verifying a large FPGA.[3 marks]What will you tell them about the differences between designing ASICs and FPGAs?Page 9 of 10(c) One of the new recruits says that simulation is a waste of time for FPGAs. What is your re-[4 marks]sponse?Page 10 of
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