ECE532 Group Report FPGA Implementation of the NES Audio Processing Unit Cedomir Segulja Bill Dai Edward S Rogers Sr Department of Electrical and Computer Engineering University of Toronto seguljac eecg toronto edu bill dai utoronto ca March 31st 2008 1 Introduction In this report we describe the work done for our ECE532 class project We designed and implemented the Nintendo Entertainment System NES Audio Processing Unit APU using an FPGA platform Furthermore for purposes of testing the developed core and for project demonstration we have design NSF player a system capable of playing NSF files using our developed core The remainder of this report is organized as follows Section 2 presents our projects goals covers background material and gives high level overview of the architecture of our system Section 3 discuss the outcome of our project and presents the software architecture of the NSF Player Section 4 provides a detail description of used components concentrating the most on the developed IP the OPB APU Section 5 explaines how we used the NES emulator to extract needed information from NSF files Section 6 provides the details about the software structure of our project Finally we include an appendix that provides additional details about the NES APU register organization 2 Overview 2 1 Goals of the Project The main goal of the project is to implement the NES Audio Processing Unit on the FPGA of Xilinx XUP VirtexTM II Pro Development Board By the ending phase of the project our APU should be able to demonstrate standalone music playing ability by using MicroBlaze as the NES CPU 1 2 2 Project Background The original CPU of Nintendo Entertainment System was 8 bit Ricoh 2A03 microprocessor based on a MOS Technology 6502 core 2 This low cost chip differed from similar product back at year 1983 in that it had the ability to handle sound serving as pseudo Audio Processing Unit APU In other words the CPU and APU were combined on one chip The processing speed of this chip is around 1 79MHZ The APU contains in total twenty 8 bit memory mapped registers The NES APU is composed of five channels These included two pulse wave channels of variable duty cycle 12 5 25 50 and 75 with a volume control of sixteen levels and hardware pitch bending supporting frequencies ranging from 54 Hz to 28 kHz Additional channels included one fixed volume triangle wave channel supporting frequencies from 27 Hz to 56 kHz one sixteen volume level white noise channel supporting two modes by adjusting inputs on a linear feedback shift register at sixteen preprogrammed frequencies and one delta pulse width modulation channel DMC with six bits of range using 1 bit delta encoding at sixteen preprogrammed sample rates from 4 2 kHz to 33 5 kHz The DMC channel used DMA to fetch previously stored samples This final channel was also capable of playing standard pulsecode modulation PCM sound by writing individual 7 bit values at timed intervals The complete functional description of the NES APU can be found in 6 8 9 7 2 3 System Description The system architecture is shown in Figure 1 The OPB Audio Processing Unit APU represents the implementation of the the NES APU To convert digital output to analog signals the on board AC97 codec is used MicroBlaze runing the APU Driver simulates the NES CPU and drives the OPB APU Memory samples for the DMC channel are stored in the BRAM which is accessed by the OPB APU through the OPB BRAM controller OPB Microprocessor Debug Module MDM is used for debugging and download UART Lite was used through the developement process it is obsolete in the final design List of used IPs is shown in Table 1 We have designed and implemented the OPB APU core which is in detail described in section 4 3 Also created software APU Driver is described in section 4 8 2 Figure 1 System Block Diagram IP Name MicroBlaze Processor On Chip Peripheral BUS OPB OPB Audio Processing Unit APU OPB Block RAM BRAM Interface Controller Block RAM BRAM Block Digital Clock Manager DCM Module OPB Microprocessor Debug Module MDM OPB UART Lite APU Driver Hardware Software IP Hardware IP Hardware IP Hardware IP Used Modified Created Used Xilinx IP Used Xilinx IP Created Modified Hardware IP Used Xilinx IP Hardware IP Used Xilinx IP Hardware IP Used Xilinx IP Hardware IP Used Xilinx IP Hardware IP Software IP Used Xilinx IP Created Table 1 Brief description of IPs 3 Function Drives the OPB APU See section 4 1 System backbone See section 4 2 NES APU implementation See section 4 3 Memory controller for the DMC dedicated memory See section 4 4 DMC dedicated memory See section 4 4 Used to derive system and NES CPU clock See section 4 5 Used for debugging and executable download See section 4 6 Used for debugging See section 4 7 Simulates the NES CPU See section 4 8 3 Outcome We have successfuly implemented the NES Audio Processing Unit on the FPGA The developed IP was tested using series of microbenchmarks Furthermore for in depth testing and for the purposes of the project demo we have designed and implemented NSF player a system which plays NSF files using our developed IP NES Sound Format NSF file is a sound data file containing instructions for the Nintendo Entertainment System NES sound hardware The overwiev of the NSF Player system is given next 3 1 NSF Player NSF Player is the system which utilizes the implemented system for playing NSF files Software flow chart of the NSF Player is displayed on Figure 2 The input is an NSF file The file is translated in the form plausible for interpreting by the MicroBlaze Information about used NSF emulator and modification of it are described in section 5 The generated file music h is compiled with the apu driver c which implements the APU Driver Finally using the Xilinx Microprocessor Debugger XMD and the JTAG cable the executable is downloaded on the FPGA MicroBlaze is running XMD Stub which allows as to download and run the executable on the fly The whole process is automatized by the script which as an input takes the NSF file As shown in Figure 2 the NES emulator also generates the out wav file This is a waveform audio file and it is used for comparison with the music played on the board Our final results is that for many examples the music played on the board is very similar indentical to the waveform file played back on the computer Figure 2 NSF Player Software Flow 4 4 Description of the Blocks This section provides detail information about used IP blocks The created IPs OPB