15 213 The course that gives CMU its Zip The Memory Hierarchy Sep 30 2003 Topics class11 ppt Storage technologies and trends Locality of reference Caching in the memory hierarchy Random Access Memory RAM Key features RAM is traditionally packaged as a chip Basic storage unit is normally a cell one bit per cell Multiple RAM chips form a memory Static RAM SRAM Each cell stores a bit with a four or six transistor circuit Retains value indefinitely as long as it is kept powered Relatively insensitive to electrical noise EMI radiation etc Faster and more expensive than DRAM Dynamic RAM DRAM 2 Each cell stores bit with a capacitor One transistor is used for access Value must be refreshed every 10 100 ms More sensitive to disturbances EMI radiation than SRAM Slower and cheaper than SRAM 15 213 F 03 SRAM vs DRAM Summary Tran per bit Access Needs Needs time refresh EDC Cost Applications SRAM 4 or 6 1X No Maybe 100x cache memories DRAM 1 10X Yes Yes 1X Main memories frame buffers 3 15 213 F 03 Conventional DRAM Organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 0 addr to CPU 2 3 0 2 bits rows memory controller 1 cols 1 supercell 2 1 2 8 bits 3 data 4 internal row buffer 15 213 F 03 Reading DRAM Supercell 2 1 Step 1 a Row access strobe RAS selects row 2 Step 1 b Row 2 copied from DRAM array to row buffer 16 x 8 DRAM chip 0 RAS 2 2 2 3 0 addr rows memory controller 1 cols 1 2 8 3 data 5 internal row buffer 15 213 F 03 Reading DRAM Supercell 2 1 Step 2 a Column access strobe CAS selects column 1 Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to the CPU 16 x 8 DRAM chip 0 CAS 1 2 rows memory controller supercell 2 1 2 3 0 addr To CPU 1 cols 1 2 8 3 data 6 supercell 2 1 internal row buffer 15 213 F 03 Memory Modules addr row i col j supercell i j DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs DRAM 7 bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 bits 0 7 0 64 bit doubleword at main memory address A Memory controller 64 bit doubleword 7 15 213 F 03 Enhanced DRAMs DRAM Cores with better interface logic and faster I O Synchronous DRAM SDRAM Uses a conventional clock signal instead of asynchronous control Double data rate synchronous DRAM DDR SDRAM Double edge clocking sends two bits per cycle per pin RamBus DRAM RDRAM Uses faster signaling over fewer wires source directed clocking with a Transaction oriented interface protocol Obsolete Technologies Fast page mode DRAM FPM DRAM Allowed re use of row addresses Extended data out DRAM EDO DRAM Enhanced FPM DRAM with more closely spaced CAS signals Video RAM VRAM Dual ported FPM DRAM with a second concurrent serial interface Extra functionality DRAMS CDRAM GDRAM Added SRAM CDRAM and support for graphics operations GDRAM 8 15 213 F 03 Nonvolatile Memories DRAM and SRAM are volatile memories Lose information if powered off Nonvolatile memories retain value even if powered off Read only memory ROM programmed during production Magnetic RAM MRAM stores bit magnetically in development Ferro electric RAM FERAM uses a ferro electric dielectric Programmable ROM PROM can be programmed once Eraseable PROM EPROM can be bulk erased UV X Ray Electrically eraseable PROM EEPROM electronic erase capability Flash memory EEPROMs with partial sector erase capability Uses for Nonvolatile Memories 9 Firmware programs stored in a ROM BIOS controllers for disks network cards graphics accelerators security subsystems Solid state disks flash cards memory sticks etc Smart cards embedded systems appliances Disk caches 15 213 F 03 Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address data and control signals Buses are typically shared by multiple devices CPU chip register file ALU system bus bus interface 10 I O bridge memory bus main memory 15 213 F 03 Memory Read Transaction 1 CPU places address A on the memory bus register file eax Load operation movl A eax ALU I O bridge bus interface 11 A main memory 0 x A 15 213 F 03 Memory Read Transaction 2 Main memory reads A from the memory bus retrieves word x and places it on the bus register file eax Load operation movl A eax ALU I O bridge bus interface 12 x main memory 0 x A 15 213 F 03 Memory Read Transaction 3 CPU read word x from the bus and copies it into register eax register file eax x Load operation movl A eax ALU I O bridge bus interface 13 main memory 0 x A 15 213 F 03 Memory Write Transaction 1 CPU places address A on bus Main memory reads it and waits for the corresponding data word to arrive register file eax y Store operation movl eax A ALU I O bridge bus interface 14 A main memory 0 A 15 213 F 03 Memory Write Transaction 2 CPU places data word y on the bus register file eax y Store operation movl eax A ALU I O bridge bus interface 15 y main memory 0 A 15 213 F 03 Memory Write Transaction 3 Main memory reads data word y from the bus and stores it at address A register file eax y Store operation movl eax A ALU I O bridge bus interface 16 main memory 0 y A 15 213 F 03 Memory Subsystem Trends Observation A DRAM chip has an access time of about 50ns Traditional systems may need 3x longer to get the data from memory into a CPU register Modern systems integrate the memory controller onto the CPU chip Latency matters DRAM and SRAM densities increase and so does the soft error rate 17 Traditional error detection correction EDC is a must have 64bit of data plus 8bits of redundancy allow any 1 bit error to be corrected and any 2 bit error is guaranteed to be detected EDC is increasingly needed for SRAMs too ChipKill capability can correct all bits supplied by one failing memory chip will become standard soon 15 213 F 03 Disk Geometry Disks consist of platters each with two surfaces Each surface consists of concentric rings called tracks Each track consists of sectors separated by gaps tracks surface track k gaps spindle sectors 18 15 213 F 03 Disk Geometry Muliple Platter View Aligned tracks form a cylinder cylinder k surface 0 platter 0 surface 1 surface 2 platter 1 surface 3 surface 4 platter 2 surface 5 spindle 19 15 213 F 03 Disk Capacity Capacity maximum number of bits that can be stored Vendors express capacity in units of gigabytes GB where 1 GB 109 …
View Full Document
Unlocking...