15 213 Virtual Memory October 26 2000 Topics Motivations for VM Address translation Accelerating translation with TLBs class18 ppt Motivations for Virtual Memory a Cache for the Disk Use Physical DRAM as Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory Each process with its own address space Only active code and data is actually in memory Allocate more memory to process as needed Provide Protection One process can t interfere with another because they operate in different address spaces User process cannot access privileged information different sections of address spaces have different permissions class18 ppt 2 CS 213 F 00 Motivation 1 DRAM a Cache for Disk Full address space is quite large 4 000 000 000 4 billion bytes 32 bit addresses 64 bit addresses 16 000 000 000 000 000 000 16 quintillion bytes Disk storage is 156X cheaper than DRAM storage 8 GB of DRAM 10 000 8 GB of disk 64 To access large amounts of data in a cost effective manner the bulk of the data must be stored on disk 4 MB 400 SRAM class18 ppt 256 MB 320 DRAM 3 8 GB 64 Disk CS 213 F 00 Levels in Memory Hierarchy cache CPU CPU regs regs Register size speed Mbyte line size 32 B 3 ns 8B 8B C a c h e 32 B Cache 32 KB 4MB 6 ns 100 MB 32 B virtual memory Memory Memory Memory 128 MB 60 ns 1 25 MB 4 KB 4 KB disk disk Disk Memory 30 GB 8 ms 0 008 MB larger slower cheaper class18 ppt 4 CS 213 F 00 DRAM vs SRAM as a Cache DRAM vs disk is more extreme than SRAM vs DRAM Access latencies DRAM 10X slower than SRAM Disk 100 000X slower than DRAM Importance of exploiting spatial locality First byte is 100 000X slower than successive bytes on disk vs 4X improvement for page mode vs regular accesses to DRAM Bottom line Design decisions made for DRAM caches driven by enormous cost of misses SRAM class18 ppt DRAM 5 Disk CS 213 F 00 Impact of These Properties on Design If DRAM was to be organized similar to an SRAM cache how would we set the following design parameters Line size Large since disk better at transferring large blocks Associativity High to mimimize miss rate Write through or write back Write back since can t afford to perform small writes to disk What would the impact of these choices be on miss rate Extremely low 1 hit time Must match cache DRAM performance miss latency Very high 20ms tag storage overhead Low relative to block size class18 ppt 6 CS 213 F 00 Loc atin SRAM Cache Tag stored with cache line g an Maps from cache block to memory blocks Obj From cached to uncached form No tag for block not in cache ect Hardware retrieves information Cache in atags can quickly match against multiple Data Ca 0 Tag D 243 Object Name X 17 X che 1 X N 1 class18 ppt 7 J 105 CS 213 F 00 Locating an Object in a Cache cont DRAM Cache Each allocate page of virtual memory has entry in page table Mapping from virtual pages to physical pages From uncached form to cached form Page table entry even if page not in memory Specifies disk address OS retrieves information Page Table Cache Location Data Object Name D 0 0 243 X J On Disk 1 17 105 X class18 ppt 1 8 N 1 CS 213 F 00 A System with Physical Memory Only Examples most Cray machines early PCs nearly all embedded systems etc Memory Physical Addresses 0 1 CPU N 1 Addresses generated by the CPU point directly to bytes in physical memory class18 ppt 9 CS 213 F 00 A System with Virtual Memory Examples Memory workstations servers modern PCs etc Virtual Addresses 0 1 Page Table Physical Addresses 0 1 CPU P 1 N 1 Disk Address Translation Hardware converts virtual addresses to physical addresses via an OS managed lookup table page table class18 ppt 10 CS 213 F 00 Page Faults Similar to Cache Misses What if an object is on disk rather than in memory Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory current process suspends others can resume OS has full control over placement etc Before fault Virtual Addresses After fault Memory Memory Page Table Page Table Physical Addresses Virtual Addresses CPU Physical Addresses CPU Disk class18 ppt Disk 11 CS 213 F 00 Servicing a Page 1 Initiate Block Read Fault Processor Signals Controller Processor Processor Reg Read block of length P starting at disk address X and store starting at memory address Y Cache Cache Read Occurs Direct Memory Access DMA Under control of I O controller Memory I O Memory I Obus bus 2 DMA Transfer Memory Memory I O Controller Signals Completion I O I O controller controller disk Disk Interrupt processor OS resumes suspended process class18 ppt 3 Read Done 12 CS 213 F 00 disk Disk Motivation 2 Memory Multiple processesManagement can reside in physical memory How do we resolve address conflicts what if two processes access something at the same address kernel virtual memory stack esp Memory mapped region forshared libraries Linux x86 process memory image class18 ppt memory invisible to user code runtime heap via malloc 0 the brk ptr uninitialized data bss initialized data data program text text forbidden 13 CS 213 F 00 Solution Separate Virtual Addr Spaces Virtual and physical address spaces divided into equal sized blocks blocks are called pages both virtual and physical Each process has its own virtual address space operating system controls how virtual pages as assigned to physical memory Virtual Address Space for Process 1 Virtual Address Space for Process 2 0 Address Translation 0 VP 1 VP 2 PP 2 N 1 PP 7 0 N 1 class18 ppt VP 1 VP 2 Physical Address Space DRAM e g read only library code PP 10 M 1 14 CS 213 F 00 Contrast Macintosh Memory Model MAC OS 1 9 Does not use traditional virtual memory Shared Address Space P1 Pointer Table Process P1 A B Handles P2 Pointer Table C Process P2 D E All program objects accessed through handles Indirect reference through pointer table Objects stored in shared global address space class18 ppt 15 CS 213 F 00 Macintosh Memory Management Allocation Deallocation Similar to free list management of malloc free Compaction Can move any object and just update the unique pointer in pointer table P1 Pointer Table Shared Address Space B Process P1 A Handles P2 Pointer Table Process P2 C D E class18 ppt 16 CS 213 F 00 Mac vs VM Based Memory Allocating deallocating Mgmt and moving memory can be accomplished by both techniques Block sizes Mac variable sized may be very small or very large VM
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