Intel P6 Bob Bob Collwel s Collwel s Chip Chip CMU CMU Alumni Alumni 15 213 Internal Designation for Successor to Pentium The course that gives CMU its Zip Which had internal designation P5 Fundamentally Different from Pentium P6 Linux Memory System March 23 2004 Out of order superscalar operation Designed to handle server applications Requires high performance memory system Resulting Processors Topics PentiumPro 1996 Pentium II 1997 P6 address translation Linux memory management Linux page fault handling Memory mapping Incorporated MMX instructions special instructions for parallel processing L2 cache on same chip Pentium III 1999 2 class19 ppt P6 Memory System 32 bit address space Incorporated Streaming SIMD Extensions More instructions for parallel processing 15 213 S 04 Review of Abbreviations 4 KB page size L1 L2 and TLBs DRAM 4 way set associative external system bus e g PCI L1 i cache TLBI TLB index TLBT TLB tag VPO virtual page offset VPN virtual page number 32 entries 8 sets Data TLB cache bus instruction fetch unit Components of the virtual address VA Inst TLB L2 cache bus interface unit Symbols inst TLB data TLB L1 d cache 64 entries 16 sets Components of the physical address PA PPO physical page offset same as VPO PPN physical page number CO byte offset within cache line CI cache index CT cache tag L1 i cache and d cache 16 KB 32 B line size 128 sets L2 cache unified processor package 3 128 KB 2 MB 15 213 S 04 4 Page 1 15 213 S 04 Overview of P6 Address Translation IA32 Segmented VM Overview 32 result CPU 20 VPN 12 virtual address VA VPO L1 128 sets 4 lines set TLB hit TLB 16 sets 4 entries set 10 10 VPN1 VPN2 20 PPN PDE PDBR 6 15 213 S 04 5 P6 2 level Page Table Structure Page directory 1024 4 byte page directory entries PDEs that point to page tables one page directory per process page page directory must be in directory memory when its process is 1024 running PDEs always pointed to by PDBR Page tables 1024 4 byte page table entries PTEs that point to pages page tables can be paged in and out 7 L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 and DRAM 20 CT 12 PPO 7 5 CI CO physical address PA PTE Page tables 15 213 S 04 P6 Page Directory Entry PDE Up to 1024 page tables 31 12 11 Page table physical base addr 1024 PTEs 9 Avail 8 7 G PS 6 5 A 4 3 2 1 0 CD WT U S R W P 1 Page table physical base address 20 most significant bits of physical page table address forces page tables to be 4KB aligned Avail These bits available for system programmers G global page don t evict from TLB on task switch PS page size 4K 0 or 4M 1 A accessed set by MMU on reads and writes cleared by software CD cache disabled 1 or enabled 0 WT write through or write back cache policy for this page table U S user or supervisor mode access R W read only or read write access P page table is present in memory 1 or not 0 1024 PTEs 1024 PTEs 31 1 Available for OS page table location in secondary storage 15 213 S 04 8 Page 2 0 P 0 15 213 S 04 P6 Page Table Entry PTE 31 12 11 Page physical base address 9 Avail 8 7 6 5 G 0 D A 4 3 2 How P6 Page Tables Map Virtual Addresses to Physical Ones 1 0 10 VPN1 CD WT U S R W P 1 word offset into page directory Page base address 20 most significant bits of physical page address forces pages to be 4 KB aligned Avail available for system programmers G global page don t evict from TLB on task switch D dirty set by MMU on writes A accessed set by MMU on reads and writes CD cache disabled or enabled WT write through or write back cache policy for this page U S user supervisor R W read write P page is present in physical memory 1 or not 0 31 1 Available for OS page location in secondary storage PTE PDBR physical address of page directory 0 physical address of page table base if P 1 20 P 0 PPN 10 Virtual address word offset into physical and virtual page page table PDE 4Mbyte PDE s 11 12 VPO word offset into page table page directory 15 213 S 04 9 10 VPN2 physical address of page base if P 1 12 PPO Physical address 15 213 S 04 Support for 4Mbyte Pages 15 213 S 04 12 Page 3 15 213 S 04 Representation of VM Address Space PT 3 Page Directory P 1 M 1 P 1 M 1 P 0 M 0 P 0 M 1 PT 2 PT 0 P 1 M 1 P 0 M 0 P 1 M 1 P 0 M 1 P 1 M 1 P 0 M 0 P 1 M 1 P 0 M 1 P 0 M 1 P 0 M 1 P 0 M 0 P 0 M 0 Page 14 Problem PagePage table storage overhead is a function of the virtual address space size Page 13 Page 12 Page 11 VPN Page 10 Page 9 Page 8 Page 7 Page 5 16 page virtual address space Page 4 Mem Addr Page 3 Disk Addr Page 2 Flags In Mem Page 0 On Disk Unmapped 15 213 S 04 P6 TLB 32 result CPU 12 virtual address VA VPO L1 miss PTE 1 1 PD V Structure of the data TLB 20 PPN PDE 16 Tag PDE PTE page directory or page table entry TLB 16 sets 4 entries set 10 10 VPN1 VPN2 32 PDE PTE V indicates a valid 1 or invalid 0 TLB entry PD is this entry a PDE 1 or a PTE 0 tag disambiguates entries cached in the same set L1 128 sets 4 lines set TLB hit TLB miss TLB entry not all documented so this is speculative L2 and DRAM L1 hit 16 4 TLBT TLBI 15 213 S 04 14 P6 TLB Translation PDBR 15 PPN TAG Page 1 P Is entry in physical memory M Has this part of VA space been mapped 20 VPN Hit Hash Page 6 Simplified Example 13 Aside Inverted Page Tables Page 15 20 CT 12 PPO 16 sets 4 entries set 7 5 CI CO physical address PA Page tables 15 213 S 04 16 Page 4 entry entry entry entry entry entry entry entry entry entry entry entry entry entry set 0 set 1 set 2 entry entry set 15 15 213 S 04 Translating with the P6 TLB P6 Page Table Translation 32 result CPU 1 Partition VPN into TLBT and TLBI CPU 2 Is the PTE for VPN cached in set TLBI 12 virtual address VPO 20 VPN 16 4 TLBT TLBI 1 TLB miss PTE TLB hit 3 20 PPN 12 PPO …
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