Intel P6 15 213 Internal Designation for Successor to Pentium The course that gives CMU its Zip Fundamentally Different from Pentium P6 Linux Memory System Mar 20 2003 Out of order superscalar operation Designed to handle server applications z Requires high performance memory system Resulting Processors Topics Which had internal designation P5 P6 address translation Linux memory management Linux page fault handling memory mapping PentiumPro 1996 Pentium II 1997 z Incorporated MMX instructions special instructions for parallel processing z L2 cache on same chip Pentium III 1999 z Incorporated Streaming SIMD Extensions More instructions for parallel processing 2 class19 ppt P6 Memory System 32 bit address space 4 KB page size 15 213 F 03 Review of Abbreviations L1 L2 and TLBs DRAM external system bus e g PCI processor package 3 L1 i cache 32 entries 8 sets inst TLB data TLB L1 d cache Components of the virtual address VA z TLBI TLB index z TLBT TLB tag z VPO virtual page offset data TLB cache bus instruction fetch unit Symbols inst TLB L2 cache bus interface unit 4 way set associative 64 entries 16 sets z VPN virtual page number z PPO physical page offset same as VPO L1 i cache and d cache 16 KB 32 B line size 128 sets Components of the physical address PA z PPN physical page number z CO byte offset within cache line z CI cache index z CT cache tag L2 cache unified 128 KB 2 MB 15 213 F 03 4 15 213 F 03 Overview of P6 Address Translation 32 result CPU 20 VPN L1 miss L1 hit TLB miss TLB 16 sets 4 entries set 10 10 VPN1 VPN2 20 CT 12 PPO 7 5 CI CO physical address PA PTE 15 213 F 03 12 11 Page table physical base addr 1024 PTEs 1024 PTEs 1024 4 byte page table entries PTEs that point to pages page tables can be paged in and out 9 Avail 8 7 G PS 6 5 A 4 3 2 1 15 213 F 03 6 P6 Page Table Entry PTE 0 31 CD WT U S R W P 1 31 1 Available for OS page table location in secondary storage 9 Avail 8 7 6 5 G 0 D A 4 3 2 1 0 CD WT U S R W P 1 Page base address 20 most significant bits of physical page address forces pages to be 4 KB aligned Avail available for system programmers G global page don t evict from TLB on task switch D dirty set by MMU on writes A accessed set by MMU on reads and writes CD cache disabled or enabled WT write through or write back cache policy for this page U S user supervisor R W read write P page is present in physical memory 1 or not 0 0 31 P 0 15 213 F 03 12 11 Page physical base address Page table physical base address 20 most significant bits of physical page table address forces page tables to be 4KB aligned Avail These bits available for system programmers G global page don t evict from TLB on task switch PS page size 4K 0 or 4M 1 A accessed set by MMU on reads and writes cleared by software CD cache disabled 1 or enabled 0 WT write through or write back cache policy for this page table U S user or supervisor mode access R W read only or read write access P page table is present in memory 1 or not 0 7 1024 PTEs Page tables P6 Page Directory Entry PDE 31 1024 4 byte page directory entries PDEs that point to page tables one page directory per process page page directory must be in directory memory when its process is 1024 running PDEs always pointed to by PDBR Page tables 20 PPN PDE L1 128 sets 4 lines set TLB hit Up to 1024 page tables Page directory 12 virtual address VA VPO 16 4 TLBT TLBI PDBR 5 L2 and DRAM P6 2 level Page Table Structure 1 Available for OS page location in secondary storage 8 0 P 0 15 213 F 03 Representation of Virtual Address Space How P6 Page Tables Map Virtual Addresses to Physical Ones 10 VPN1 10 VPN2 word offset into page directory 12 VPO Virtual address P 0 M 0 P 1 M 1 P 0 M 1 Page Directory word offset into physical and virtual page word offset into page table page directory P 1 M 1 PT 3 P 1 M 1 P 1 M 1 P 0 M 0 P 0 M 1 page table P 1 M 1 PT 2 PT 0 P 0 M 0 P 1 M 1 P 0 M 1 P 0 M 1 P 0 M 1 P 0 M 0 P 0 M 0 physical address of page base if P 1 PTE PDE PDBR physical address of page directory physical address of page table base if P 1 Physical address 15 213 F 03 10 P6 TLB Translation 12 virtual address VA VPO L1 miss L1 128 sets 4 lines set TLB hit Page 9 Page 8 Page 7 Page 6 Page 5 16 page virtual address space Page 4 Mem Addr Page 3 Disk Addr In Mem Page 1 On Disk Page 0 P Is entry in physical memory M Has this part of VA space been mapped Unmapped 15 213 F 03 32 16 1 1 PDE PTE Tag PD V V indicates a valid 1 or invalid 0 TLB entry PD is this entry a PDE 1 or a PTE 0 tag disambiguates entries cached in the same set PDE PTE page directory or page table entry z Structure of the data TLB TLB 16 sets 4 entries set PTE Page 10 TLB entry not all documented so this is speculative 20 PPN PDBR 11 L2 andDRAM L1 hit 16 4 TLBT TLBI PDE Page 11 P6 TLB 32 result 10 10 VPN1 VPN2 Page 12 Page 2 9 TLB miss Page 13 Simplified Example 12 PPO PPN 20 VPN Page 14 Flags 20 CPU Page 15 20 CT 12 PPO 7 5 CI CO physical address PA Page tables 15 213 F 03 12 16 sets 4 entries set entry entry entry entry entry entry entry entry entry entry entry entry entry entry set 0 set 1 set 2 entry entry set 15 15 213 F 03 P6 page table translation Translating with the P6 TLB 1 Partition VPN into TLBT and TLBI CPU 2 Is the PTE for VPN cached in set TLBI 12 virtual address 20 VPN VPO 16 4 TLBT TLBI 1 TLB miss 2 PDE PTE TLB hit 3 20 PPN 12 PPO physical address page table translation 4 3 Yes then build physical address 4 No then read PTE and PDE if not cached from memory and build physical address 15 213 F 03 Translating with the P6 Page Tables case 1 1 12 VPO 20 PPN VPN1 VPN2 12 PPO Mem PTE p 1 PDBR Page directory Disk 15 Page table 32 result …
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