Random Access Memory RAM 15 213 Key features The course that gives CMU its Zip The Memory Hierarchy Sept 29 2006 Static RAM SRAM SRAM Topics RAM is traditionally packaged as a chip Basic storage unit is normally a cell one bit per cell Multiple RAM chips form a memory Storage technologies and trends Locality of reference Caching in the memory hierarchy Each cell stores a bit with a four or six transistor circuit Retains value indefinitely as long as it is kept powered Relatively insensitive to electrical noise EMI radiation etc Faster and more expensive than DRAM Dynamic RAM DRAM DRAM Each cell stores bit with a capacitor One transistor is used for access Value must be refreshed every 10 100 ms More sensitive to disturbances EMI radiation than SRAM Slower and cheaper than SRAM 15 213 F 06 2 class10 ppt SRAM vs DRAM Summary Conventional DRAM Organization d x w DRAM Tran per bit Access Needs Needs time refresh EDC dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip Cost Applications cols 0 SRAM 4 or 6 1X No Maybe 100x cache memories DRAM 1 10X Yes Yes 1X Main memories frame buffers 2 bits 1 2 3 0 addr 1 rows memory controller supercell 2 1 2 to CPU 8 bits 3 data 3 15 213 F 06 4 internal row buffer 15 213 F 06 Reading DRAM Supercell 2 1 Reading DRAM Supercell 2 1 Step 1 a Row access strobe RAS RAS selects row 2 Step 2 a Column access strobe CAS CAS selects column 1 Step 1 b Row 2 copied from DRAM array to row buffer Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to the CPU 16 x 8 DRAM chip 16 x 8 DRAM chip cols 0 RAS 2 2 1 cols 2 3 2 0 addr data 3 0 1 2 supercell 2 1 3 8 2 rows memory controller 2 1 addr To CPU 1 rows memory controller 0 CAS 1 8 3 data internal row buffer 5 15 213 F 06 Memory Modules supercell 2 1 6 internal row buffer 15 213 F 06 Enhanced DRAMs addr row i col j DRAM Cores with better interface logic and faster I O supercell i j Synchronous DRAM SDRAM Double data rate synchronous DRAM DDR SDRAM RamBus DRAM RDRAM Uses a conventional clock signal instead of asynchronous control DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs DRAM 7 Double edge clocking sends two bits per cycle per pin Uses faster signaling over fewer wires source directed clocking with a Transaction oriented interface protocol Obsolete Technologies bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 bits 0 7 0 64 bit doubleword at main memory address A Fast page mode DRAM FPM DRAM Extended data out DRAM EDO DRAM Video RAM VRAM Extra functionality DRAMS CDRAM GDRAM Allowed re use of row addresses Enhanced FPM DRAM with more closely spaced CAS signals Memory controller Dual ported FPM DRAM with a second concurrent serial interface Added SRAM CDRAM and support for graphics operations GDRAM 64 bit doubleword 7 15 213 F 06 8 15 213 F 06 Traditional Bus Structure Connecting CPU and Memory Nonvolatile Memories DRAM and SRAM are volatile memories A bus is a collection of parallel wires that carry address data and control signals Lose information if powered off Nonvolatile memories retain value even if powered off Read only memory ROM programmed during production Magnetic RAM MRAM stores bit magnetically in development Ferro electric RAM FERAM uses a ferro electric dielectric Programmable ROM PROM can be programmed once Eraseable PROM EPROM can be bulk erased UV X Ray Electrically eraseable PROM EEPROM electronic erase capability Flash memory EEPROMs with partial sector erase capability Buses are typically shared by multiple devices CPU chip register file ALU Uses for Nonvolatile Memories memory bus system bus Firmware programs stored in a ROM BIOS controllers for disks network cards graphics accelerators security subsystems Solid state disks flash cards memory sticks etc Smart cards embedded systems appliances Disk caches 15 213 F 06 9 main memory I O bridge bus interface 15 213 F 06 10 Memory Read Transaction 1 Memory Read Transaction 2 CPU places address A on the memory bus Main memory reads A from the memory bus retrieves word x and places it on the bus register file eax ALU eax I O bridge bus interface 11 register file Load operation movl A eax A main memory 0 x ALU I O bridge bus interface A 15 213 F 06 Load operation movl A eax 12 x main memory 0 x A 15 213 F 06 Memory Read Transaction 3 Memory Write Transaction 1 CPU read word x from the bus and copies it into register eax eax CPU places address A on bus Main memory reads it and waits for the corresponding data word to arrive register file eax x register file Load operation movl A eax ALU eax y Store operation movl eax A ALU main memory 0 I O bridge bus interface 15 213 F 06 A main memory 0 bus interface A x 13 I O bridge A 15 213 F 06 14 Memory Write Transaction 2 Memory Write Transaction 3 CPU places data word y on the bus Main memory reads data word y from the bus and stores it at address A register file eax y ALU eax I O bridge bus interface 15 register file Store operation movl eax A y y main memory 0 ALU I O bridge bus interface A 15 213 F 06 Store operation movl eax A 16 main memory 0 y A 15 213 F 06 Memory Subsystem Trends Disk Geometry Observation A DRAM chip has an access time of about 50ns Traditional systems may need 3x longer to get the data from memory into a CPU register Disks consist of platters platters each with two surfaces surfaces z Modern systems integrate the memory controller onto the CPU chip Latency matters Each track consists of sectors separated by gaps gaps Each surface consists of concentric rings called tracks tracks tracks z DRAM and SRAM densities increase and so does the softsoft error rate surface track k Traditional error detection correction EDC is a must have 64bit of data plus 8bits of redundancy allow any 1 bit error to be corrected and any 2 bit error is guaranteed to be detected EDC is increasingly needed for SRAMs too ChipKill capability can correct all bits supplied by one failing memory chip will become standard soon gaps spindle sectors 15 213 F 06 17 15 213 F 06 18 Disk Geometry Muliple Platter View Disk Capacity Aligned tracks form a cylinder Capacity maximum number of bits that can be stored cylinder k Vendors express capacity in units of gigabytes GB where 1 GB 109 Bytes Lawsuit pending Claims deceptive advertising Capacity is determined by these technology factors …
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