Announcements 15 213 Exam Thursday two days from now The course that gives CMU its Zip Main Memory and Caches Sept 23 2008 Calculator policy DRAM as main memory Locality of reference Caches Byte Oriented Memory Organization 0 FF F Normal R Mem Reg R Mem Reg R Register R specifies memory address movl ecx eax Programs Refer to Virtual Memory Addresses Conceptually very large array of bytes Actually implemented with hierarchy of different memory types System provides address space private to particular process Program being executed Program can clobber its own data but not that of others Displacement D R Mem Reg R D Mem Reg R D Register R specifies start of memory region Constant displacement D specifies offset Compiler RunRun Time System Control Allocation 3 movl 8 ebp edx Where different program objects should be stored All allocation within single virtual address space 15 213 F 08 From class02 ppt 15 213 F 08 Simple Addressing Modes Talking through a problem can include pictures not code 2 lecture 09 ppt 00 Calculators will not be needed on the exam hence forbidden Collaboration reminder Writing code together counts as sharing code forbidden Topics In class See exams page on class website for info and old exams 4 15 213 F 08 From class04 ppt 1 Traditional Bus Structure Connecting CPU and Memory Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address data and control signals A bus is a collection of parallel wires that carry address data and control signals Buses are typically shared by multiple devices Buses are typically shared by multiple devices CPU CPU register file register file ALU ALU memory bus memory bus main memory bus interface 5 15 213 F 08 main memory bus interface 6 15 213 F 08 Memory Read Transaction 1 Memory Read Transaction 2 Step 1 CPU places address A on the memory bus with signal indicating read read Steps 22 4 Main memory reads A from the memory bus retrieves word x and places it on the bus CPU CPU register file eax ALU eax A bus interface 7 register file Load operation movl A eax main memory 0 x Load operation movl A eax ALU x bus interface A 15 213 F 08 8 main memory 0 x A 15 213 F 08 2 Memory Read Transaction 3 Memory Write Transaction 1 Step 5 CPU reads word x from the bus and copies it into register eax eax Step 1 CPU places address A on the memory bus with signal indicating write write CPU CPU register file eax xx register file Load operation movl A eax ALU eax y Store operation movl eax A ALU main memory 0 bus interface x A bus interface A 9 main memory 0 15 213 F 08 A 10 15 213 F 08 Memory Write Transaction 2 Memory Write Transaction 3 Step 2 CPU places data word y on the memory bus Steps 33 4 Main memory reads data word y from the bus and stores it at address A CPU CPU register file eax y ALU eax y bus interface 11 register file Store operation movl eax A y main memory 0 Store operation movl eax A ALU main memory 0 bus interface A 15 213 F 08 12 y A 15 213 F 08 3 Random Access Memory RAM Conventional DRAM Organization Key features d x w DRAM RAM is traditionally packaged as a chip Basic storage unit is normally a cell one bit per cell Multiple RAM chips form a memory dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip cols Dynamic RAM DRAM DRAM Common technology for main memory Organized in two dimensions rows and columns 0 2 bits Consequence 2nd 2 3 0 addr To access select row then select column 1 1 rows memory controller row access faster than different column row Some technical details 2 to CPU Each cell stores bit with a capacitor One transistor is used for access Value must be refreshed every 10 100 ms 3 8 bits data 13 15 213 F 08 internal row buffer 14 15 213 F 08 Conventional DRAM Organization Conventional DRAM Organization d x w DRAM d x w DRAM dw total bits organized as d supercells of size w bits dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 16 x 8 DRAM chip cols 2 bits addr cols 0 1 2 3 0 0 1 2 3 1 4 5 6 7 0 2 bits memory controller 2 3 8 12 9 memory controller 10 11 1 2 to CPU 13 14 15 8 bits data 15 3 rows to CPU 8 bits 2 0 addr rows 1 3 data internal row buffer 15 213 F 08 16 internal row buffer 15 213 F 08 4 Conventional DRAM Organization Step 1 a Row access strobe RAS RAS selects row 2 d x w DRAM Reading DRAM Supercell 9 2 1 dw total bits organized as d supercells of size w bits Step 1 b Row 2 copied from DRAM array to row buffer 16 x 8 DRAM chip 16 x 8 DRAM chip cols 0 2 bits 1 cols 2 3 0 RAS 2 2 0 1 2 addr addr 1 1 rows memory controller 2 rows memory controller supercell 9 2 1 to CPU 2 3 8 bits 3 8 data data internal row buffer 17 15 213 F 08 Reading DRAM Supercell 9 2 1 internal row buffer 18 addr row i col j supercell i j Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to the CPU DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAM chips 16 x 8 DRAM chip DRAM 7 cols 0 CAS 1 2 1 2 15 213 F 08 Multi chip Memory Modules Step 2 a Column access strobe CAS CAS selects column 1 3 0 addr To CPU 1 bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 rows memory controller bits 0 7 2 63 supercell 2 1 3 0 8 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 3 64 bit doubleword at main memory address A Memory controller data 64 bit doubleword 19 supercell 2 1 internal row buffer 15 213 F 08 20 15 213 F 08 5 Memory access is slow Caches to the rescue Obervation Obervation memory access is slower than CPU cycles Cache A smaller faster memory that acts as a staging area for a subset of the data in a larger slower memory A DRAM chip has an access time of 30 50ns further systems may need 3x longer or more to get the data from memory into a CPU register With sub ns cycle times 100s of cycles per memory access and the gap has been growing Can Can t go to memory on every load and store approximately 1 3 of instructions are …
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