15 213 The course that gives CMU its Zip Cache Memories Oct 2 2003 Topics Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance class12 ppt Cache Memories Cache memories are small fast SRAM based memories managed automatically in hardware Hold frequently accessed blocks of main memory CPU looks first for data in L1 then in L2 then in main memory Typical system structure 2 15 213 F 03 Inserting an L1 Cache Between the CPU and Main Memory 0 1 3 15 213 F 03 General Organization of a Cache 36 7 6 2 2 2 34 222 2 2 2 34 2 2 2 34 2 2 2 34 2 2 2 34 2 2 2 34 5 7 222 5 7 222 222 5 4 5 63 7 15 213 F 03 Addressing Caches 5 5 5 5 8 9 8 9 8 9 8 9 8 9 9 2 2 2 34 222 2 2 2 34 222 2 2 2 34 222 2 2 2 34 2 2 2 34 222 2 2 2 34 8 8 5 15 213 F 03 9 Addressing Caches 5 5 5 5 8 2 2 2 34 222 2 2 2 34 8 9 8 8 9 8 8 6 9 2 2 2 34 222 2 2 2 34 222 2 2 2 34 222 2 2 2 34 9 9 15 213 F 03 9 Direct Mapped Cache Simplest kind of cache easy to build only 1 tag compare required per access Characterized by exactly one line per set 5 5 76 222 5 5 7 63 15 213 F 03 Accessing Direct Mapped Caches Set selection Use the set index bits to determine the set of interest 5 5 222 5 8 15 213 F 03 Accessing Direct Mapped Caches Line matching and word selection Line matching Find a valid line in the selected set with a matching tag Word selection Then extract the word 6 1 15 0 1 1 6 9 1 15 213 F 03 Accessing Direct Mapped Caches Line matching and word selection Line matching Find a valid line in the selected set with a matching tag Word selection Then extract the word 15 1 0 10 15 213 F 03 Direct Mapped Cache Simulation 6 6 6 6 0 6 36 76 0 1 7 8 0 15 00002 00012 01112 10002 00002 11 0 15 213 F 03 Set Associative Caches Characterized by more than one line per set 5 5 76 222 5 7 12 15 213 F 03 Accessing Set Associative Caches Set selection identical to direct mapped cache 5 5 222 5 13 15 213 F 03 Accessing Set Associative Caches Line matching and word selection must compare the tag in each valid line in the selected set 6 1 15 1 1 6 14 1 15 213 F 03 Accessing Set Associative Caches Line matching and word selection Word selection is the same as in a direct mapped cache 15 1 15 15 213 F 03 2 Way Associative Cache Simulation 6 6 6 6 0 6 36 76 0 1 7 8 0 15 00002 00012 01112 10002 00002 16 0 15 213 F 03 Why Use Middle Bits as Index 00 01 10 11 High Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle Order Bit Indexing Consecutive memory lines map to different cache lines Can hold S B E byte region of address space in cache at one time 17 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 213 F 03 Maintaining a Set Associate Cache How to decide which cache line to use in a set Least Recently Used LRU Requires lg2 E extra bits Not recently Used NRU Random Virtual vs Physical addresses The memory system works with physical addresses but it takes time to translate a virtual to a physical address So most L1 caches are virtually indexed but physically tagged 18 15 213 F 03 Multi Level Caches Options separate data and instruction caches or a unified cache 5 3 5 A 0 B 3 5 5 3 19 3 3 0 A 3 3 3C 0 A 3 B3 D 3 A 3 15 213 F 03 What about writes Multiple copies of data exist L1 L2 Main Memory Disk What to do when we write Write through Write back need a dirty bit What to do on a write miss What to do on a replacement Depends on whether it is write through or write back 20 15 213 F 03 Intel Pentium III Cache Hierarchy C 0 B 3 E 3 0 B 3 3 21 B B3 3 EE EE 33 33 D D33 15 213 F 03 Cache Performance Metrics Miss Rate Fraction of memory references not found in cache misses references Typical numbers 3 10 for L1 can be quite small e g 1 for L2 depending on size etc Hit Time Time to deliver a line in the cache to the processor includes time to determine whether the line is in the cache Typical numbers 5 1 2 clock cycle for L1 5 20 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically 50 200 cycles for main memory Trend increasing 22 15 213 F 03 Writing Cache Friendly Code Repeated references to variables are good temporal locality Stride 1 reference patterns are good spatial locality Examples cold cache 4 byte words 4 word cache blocks int sum array rows int a M N int i j sum 0 int sum array cols int a M N int i j sum 0 for i 0 i M i for j 0 j N j sum a i j return sum for j 0 j N j for i 0 i M i sum a i j return sum 23 15 213 F 03 Detecting the Cache Parameters How can one determine the cache parameters Size of cache Size of cache block Hit time Miss penalty Associatively Number of levels in memory hierarchy Complicating factors Prefetch support hardware and software Non blocking caches Hit under Miss support Superscalar processors with multiple concurrent memory operations Victim caches stream buffers line reservation 24 15 213 F 03 The Memory Mountain Read throughput read bandwidth Number of bytes read from memory per second MB s Memory mountain Measured read throughput as a function of spatial and temporal locality Compact way to characterize memory system performance 25 15 213 F 03 Memory Mountain Test Function The test function void test int elems int stride int i result 0 volatile int sink for i 0 i elems i stride result data i sink result So compiler doesn t optimize away the loop Run test elems stride and return read throughput MB s double run int size int stride double Mhz double cycles int elems size sizeof int test elems stride warm up …
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