University of Toronto ECE532 Digital Hardware Module m07 Using ModelSim to Simulate Your Designs Version for ModelSim SE 6 3e as of January 7 2009 Introduction ModelSim is a powerful HDL simulation tool that allows you to stimulate the inputs of your modules and view both outputs and internal signals It allows you to do both behavioural and timing simulation however this document will focus on behavioural simulation In behavioural simulation you can write models that will not necessarily synthesize An example is a behavioural model for the ZBT RAMs used on the Xilinx Multimedia board This code cannot be synthesized but it is intended to give a true reflection of the behaviour of the memory chip so that you can test whether your memory controller is functioning properly This module is intended as a quick intro to using ModelSim in the UofT environment Other resources for ModelSim are linked on the UofT EDK page Source Files for Examples Download and unzip the m07 zip file from the UofT EDK Tutorials page Using the ModelSim GUI While there are many things you can do with ModelSim these are the basic things you will need to get started 1 If you are using a Windows based system launch ModelSim from the Courseware directory Otherwise if you are logged in on the ECF Linux workstations make sure 7326 picton eecg utoronto ca is in your LM LICENSE FILE environment variable and then launch local packages modeltech bin vsim 2 From the Modelsim GUI change directory to your project directory which should include your design files and testbench 3 Type the following command to create a ModelSim working directory called work This is where Modelsim will compile your design to GUI menu File New Directory vlib work 4 Before simulating your design you need to compile the source files and testbench For hierarchical designs compile the lower level design blocks before the higher level design blocks To compile GUI menu Compile Compile type the following commands vlog design file v vcom design file2 vhd vlog testbench v 5 To simulate your design type the following command vsim working directory topmost module name 6 For example if your working directory is work and your design has topmost module named top GUI menu Simulate Simulate select the topmost module name from the Design tab vsim work top 1 University of Toronto ECE532 Digital Hardware Module m07 Using ModelSim to Simulate Your Designs 7 If this is a post synthesis simulation or if any Xilinx core macros are instantiated in your Verilog source code you must compile the simulation libraries before simulating Once the libraries are compiled use the L flag to reference the compiled libraries GUI add the library to reference in the Libraries tab You can open the Wave window the Signal window and the Workspace window from the main GUI by going to the View menu In the Workspace window you can expand the module s hierarchy The signals in the Signal window will correspond to the level selected in the Workspace window Expanding and selecting a level in the main ModelSim window Workspace sim tab has the same effect The signals can then be dragged and dropped from the Signals window into the Wave window for viewing If you are debugging you will probably wish to use the same set of signals every time you simulate this module You can save the format of the signals radix dividers and labels by selecting File Save Format in the Wave window This will save the format not the simulation data to a do file Sometimes you may find it useful to modify the do file by hand instead of manipulating signal names from the Wave window GUI Once the signals are in the Wave window you can Restart the simulation by typing restart force You can then run the testbench by clicking on the Run All button on the Wave window toolbar Alternately you could type run all at the ModelSim command prompt in the main ModelSim window to run the testbench As you make modifications to your HDL during debugging you will have to re compile it within ModelSim before re simulating Note that for simulation purposes re synthesizing your HDL in the Xilinx tools will have no impact besides helping to find syntax errors New to ModelSim 6 2e The optimizer VOPT is now run by default when you launch VSIM to simulate your designs This has the benefit of making your simulations run considerably faster with the side effect of making it impossible to monitor internal signals by default You can prevent VOPT from being invoked automatically by including novopt in your VCOM VLOG and VSIM invokations Alternatively you can enable optimization with increased symbol visibility for a smaller performance penalty by using the acc flag to VOPT similar to the g flag for GCC For instance when you launch VSIM you can use the command vsim voptargs acc to enable full debug access to your design A Simple Example As a basic example consider the simulation of a full adder 1 Launch the ModelSim GUI 2 Change directory in ModelSim to lab7 full adder 3 From the ModelSim command window type the following command to create a ModelSim working directory called work vlib work 4 Compile the full adder v Verilog file vlog full adder v 5 Start the simulation on the top level entity full adder vsim work full adder 2 University of Toronto ECE532 Digital Hardware Module m07 Using ModelSim to Simulate Your Designs Note that ModelSim informs you that VOPT is being run Note vsim 3812 Design is being optimized 6 Add the Wave and Workspace windows to the GUI view wave view workspace Note For earlier of versions Modelsim the workspace window was called the structure window Hence the above commands would have to be replaced as follows view wave view structure 7 Position the Wave and Worksapce windows such that they are both visible on the screen Drag the full adder block from the Workspace window onto the leftmost column of the Wave window The following five signals should be added to the leftmost column of the Workspace window full adder a full adder b full adder cin full adder sum full adder cout Note that the Visibility column in the Workspace window shows that the full adder block was optimized with acc none 8 Return to the main Modelsim GUI window Type the following commands to force the inputs to set values force a 0 force b 1 force cin 1 9 Run the simulation for 1 microsecond run 1 us 10 Return to the Wave window You should see the waveforms resulting from the simulation 11 You may repeat the above process of setting the inputs running the