15 213 P6 Linux Memory System April 5 2001 Topics class21 ppt P6 address translation Linux memory management Linux page fault handling memory mapping Intel P6 Internal Designation for Successor to Pentium Which had internal designation P5 Fundamentally Different from Pentium Out of order superscalar operation Designed to handle server applications Requires high performance memory system Resulting Processors PentiumPro 1996 Pentium II 1997 Incorporated MMX instructions special instructions for parallel processing L2 cache on same chip Pentium III 1999 Incorporated Streaming SIMD Extensions More instructions for parallel processing class21 ppt 2 CS 213 S 01 P6 memory system DRAM external system bus e g PCI L2 cache cache bus inst TLB bus interface unit instruction fetch unit data TLB L1 i cache L1 d cache processor package class21 ppt 3 32 bit address space 4 KB page size L1 L2 and TLBs 4 way set associative inst TLB 32 entries 8 sets data TLB 64 entries 16 sets L1 i cache and d cache 16 KB 32 B line size 128 sets L2 cache unified 128 KB 2 MB CS 213 S 01 Review of abbreviations Symbols Components of the virtual address VA TLBI TLB index TLBT TLB tag VPO virtual page offset VPN virtual page number Components of the physical address PA PPO physical page offset same as VPO PPN physical page number CO byte offset within cache line CI cache index CT cache tag Other PDBR Page directory base register class21 ppt 4 CS 213 S 01 Overview of P6 address translation 32 result CPU 20 VPN 12 VPO virtual address VA TLB 16 sets 4 entries set 10 10 VPN1 VPN2 PDE PDBR L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 and DRAM L1 128 sets 4 lines set TLB hit 20 PPN 20 CT 12 PPO 7 5 CI CO physical address PA PTE Page tables class21 ppt 5 CS 213 S 01 P6 2 level page table structure Page directory 1024 4 byte page directory entries PDEs that point to page tables one page directory per process page directory must be in memory when its process is running always pointed to by PDBR Page tables 1024 4 byte page table entries PTEs that point to pages page tables can be paged in and out class21 ppt 6 Up to 1024 page tables page directory 1024 PDEs 1024 PTEs 1024 PTEs 1024 PTEs CS 213 S 01 31 P6 page directory entry PDE 12 11 Page table physical base addr 9 Avail 8 7 G PS 6 5 A 4 3 2 1 0 CD WT U S R W P 1 Page table physical base address 20 most significant bits of physical page table address forces page tables to be 4KB aligned Avail available for system programmers G global page don t evict from TLB on task switch PS page size 4K 0 or 4M 1 A accessed set by MMU on reads and writes cleared by software CD cache disabled 1 or enabled 0 WT write through or write back cache policy for this page table U S user or supervisor mode access R W read only or read write access P page table is present in memory 1 or not 0 31 1 Available for OS page table location in secondary storage class21 ppt 7 0 P 0 CS 213 S 01 P6 page table entry PTE 31 12 11 Page physical base address 9 Avail 8 7 6 5 G 0 D A 4 3 2 1 0 CD WT U S R W P 1 Page base address 20 most significant bits of physical page address forces pages to be 4 KB aligned Avail available for system programmers G global page don t evict from TLB on task switch D dirty set by MMU on writes A accessed set by MMU on reads and writes CD cache disabled or enabled WT write through or write back cache policy for this page U S user supervisor R W read write P page is present in physical memory 1 or not 0 31 1 Available for OS page location in secondary storage class21 ppt 8 0 P 0 CS 213 S 01 How P6 page tables map virtual addresses to physical ones Virtual address 10 VPN1 10 VPN2 word offset into page directory 12 VPO word offset into page table page directory page table PTE PDE PDBR physical address of page directory physical address of page table base if P 1 20 physical address of page base if P 1 12 PPO PPN class21 ppt word offset into physical and virtual page 9 Physical address CS 213 S 01 Representation of Virtual Address Space PT 3 P 1 M 1 P 0 M 0 P 1 M 1 P 0 M 1 Page Directory P 1 M 1 P 1 M 1 P 0 M 0 P 0 M 1 PT 2 PT 0 P 1 M 1 P 0 M 0 P 1 M 1 P 0 M 1 P 0 M 1 P 0 M 1 P 0 M 0 P 0 M 0 Page 15 Simplified Example 16 page virtual address space Flags P Is entry in physical memory M Has this part of VA space been mapped class21 ppt 10 Page 14 Page 13 Page 12 Page 11 Page 10 Page 9 Page 8 Page 7 Page 6 Page 5 Page 4 Mem Addr Page 3 Disk Addr Page 2 In Mem Page 1 Page 0 On Disk Unmapped CS 213 S 01 P6 TLB translation 32 result CPU 20 VPN 12 VPO virtual address VA TLB 16 sets 4 entries set 10 10 VPN1 VPN2 PDE PDBR L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 andDRAM L1 128 sets 4 lines set TLB hit 20 PPN 20 CT 12 PPO 7 5 CI CO physical address PA PTE Page tables class21 ppt 11 CS 213 S 01 P6 TLB TLB entry not all documented so this is speculative 32 16 1 PTE Tag V V indicates a valid 1 or invalid 0 TLB entry tag disambiguates entries cached in the same set PTE page table entry Structure of the data TLB 16 sets 4 entries set class21 ppt entry entry entry entry entry entry entry entry entry entry entry entry entry entry set 0 set 1 set 2 entry entry set 15 12 CS 213 S 01 Translating with the P6 TLB CPU 20 VPN 12 virtual address VPO 16 4 TLBT TLBI 1 TLB miss 2 page table translation class21 ppt TLB PTE hit 3 20 PPN 12 PPO 1 Partition VPN into TLBT and TLBI 2 Is the PTE for VPN cached in set TLBI 3 Yes then build physical address 4 No then read PTE and PDE if not cached from memory and build physical address physical address 4 13 CS 213 S 01 P6 page table translation 32 result CPU 20 VPN 12 VPO virtual address VA TLB 16 sets 4 entries set 10 10 VPN1 VPN2 PDE PDBR L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 andDRAM L1 128 sets 4 lines set TLB …
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