Motivations for Virtual Memory 15 213 The course that gives CMU its Zip Virtual Memory October 30 2001 Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory Each process with its own address space Only active code and data is actually in memory Allocate more memory to process as needed Topics Motivations for VM Address translation Accelerating translation with TLBs class19 ppt Provide Protection One process can t interfere with another because they operate in different address spaces User process cannot access privileged information different sections of address spaces have different permissions class19 ppt Motivation 1 DRAM a Cache for Disk 2 CS 213 F 01 Levels in Memory Hierarchy Full address space is quite large 32 bit addresses 4 000 000 000 4 billion bytes 64 bit addresses 16 000 000 000 000 000 000 16 quintillion bytes cache Disk storage is 156X cheaper than DRAM storage 8 GB of DRAM 10 000 8 GB of disk 64 CPU CPU regs regs To access large amounts of data in a cost effective manner the bulk of the data must be stored on disk 256 MB 320 8 GB 64 4 MB 400 SRAM DRAM Register size speed Mbyte line size 32 B 3 ns 8B 8B C a c h e 32 B Cache 32 KB 4MB 6 ns 100 MB 32 B virtual memory Memory Memory Memory 128 MB 60 ns 1 25 MB 4 KB 4 KB disk disk Disk Memory 30 GB 8 ms 0 008 MB Disk larger slower cheaper class19 ppt 3 CS 213 F 01 class19 ppt 4 CS 213 F 01 DRAM vs SRAM as a Cache DRAM vs disk is more extreme than SRAM vs DRAM Access latencies DRAM 10X slower than SRAM Disk 100 000X slower than DRAM Importance of exploiting spatial locality First byte is 100 000X slower than successive bytes on disk vs 4X improvement for page mode vs regular accesses to DRAM Bottom line Design decisions made for DRAM caches driven by enormous cost of misses SRAM DRAM class19 ppt Disk 5 CS 213 F 01 Locating an Object in a Cache SRAM Cache Object Name X 7 Cache Tag Data 0 D 243 1 X J 17 105 N 1 class19 ppt If DRAM was to be organized similar to an SRAM cache how would we set the following design parameters Line size Large since disk better at transferring large blocks Associativity High to mimimize miss rate Write through or write back Write back since can t afford to perform small writes to disk What would the impact of these choices be on miss rate Extremely low 1 hit time Must match cache DRAM performance miss latency Very high 20ms tag storage overhead Low relative to block size class19 ppt 6 CS 213 F 01 Locating an Object in a Cache cont DRAM Cache Tag stored with cache line Maps from cache block to memory blocks From cached to uncached form No tag for block not in cache Hardware retrieves information can quickly match against multiple tags X Impact of These Properties on Design CS 213 F 01 Each allocate page of virtual memory has entry in page table Mapping from virtual pages to physical pages From uncached form to cached form Page table entry even if page not in memory Specifies disk address OS retrieves information Page Table Cache Location Data Object Name D 0 0 243 X J On Disk 1 X 1 N 1 17 105 class19 ppt 8 CS 213 F 01 A System with Physical Memory Only Examples A System with Virtual Memory Examples most Cray machines early PCs nearly all embedded systems etc Memory 0 1 Page Table Virtual Addresses 0 1 Physical Addresses Memory workstations servers modern PCs etc CPU Physical Addresses 0 1 CPU P 1 N 1 N 1 Disk Addresses generated by the CPU point directly to bytes in physical memory class19 ppt 9 Address Translation Hardware converts virtual addresses to physical addresses via an OS managed lookup table page table class19 ppt CS 213 F 01 Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory current process suspends others can resume OS has full control over placement etc CS 213 F 01 Servicing a Page Fault Page Faults Similar to Cache Misses What if an object is on disk rather than in memory 10 1 Initiate Block Read Processor Signals Controller Processor Processor Reg Read block of length P starting at disk address X and store starting at memory address Y 3 Read Done Cache Cache Read Occurs Before fault After fault Memory Memory Page Table Virtual Addresses Page Table Physical Addresses Virtual Addresses CPU Physical Addresses CPU Memory I O Memory I Obus bus 2 DMA Transfer Memory Memory I O Controller Signals Completion Interrupt processor OS resumes suspended process Disk class19 ppt Direct Memory Access DMA Under control of I O controller I O I O controller controller disk Disk Disk 11 CS 213 F 01 class19 ppt 12 CS 213 F 01 disk Disk Motivation 2 Memory Management Multiple processes can reside in physical memory How do we resolve address conflicts what if two processes access something at the same address kernel virtual memory stack esp Virtual and physical address spaces divided into equal sized blocks blocks are called pages both virtual and physical Each process has its own virtual address space operating system controls how virtual pages as assigned to physical memory memory invisible to user code 0 Virtual Address Space for Process 1 Memory mapped region forshared libraries Linux x86 process memory image VP 1 VP 2 PP 2 N 1 the brk ptr class19 ppt 13 CS 213 F 01 Contrast Macintosh Memory Model MAC OS 1 9 0 VP 1 VP 2 PP 10 M 1 N 1 class19 ppt 14 CS 213 F 01 Macintosh Memory Management Allocation Deallocation Does not use traditional virtual memory Shared Address Space P1 Pointer Table B P2 Pointer Table Similar to free list management of malloc free Compaction Can move any object and just update the unique pointer in pointer table Shared Address Space P1 Pointer Table A Process P1 B Process P1 C A Process P2 D Handles E P2 Pointer Table D Indirect reference through pointer table Objects stored in shared global address space 15 C Process P2 All program objects accessed through handles class19 ppt e g read only library code PP 7 Virtual Address Space for Process 2 uninitialized data bss initialized data data program text text forbidden Physical Address Space DRAM Address Translation 0 runtime heap via malloc 0 Handles Solution Separate Virtual Addr Spaces E CS 213 F 01 class19 ppt 16 CS 213 F 01 Mac vs VM Based Memory Mgmt Allocating deallocating and moving memory MAC OS X Modern Operating System can be accomplished by both techniques
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