Carnegie Mellon The Memory Hierarchy 15 213 Introduc0on to Computer Systems 9th Lecture Sep 21 2010 Instructors Randy Bryant and Dave O Hallaron 1 Carnegie Mellon Today Storage technologies and trends Locality of reference Caching in the memory hierarchy 2 Carnegie Mellon Random Access Memory RAM Key features RAM is tradi0onally packaged as a chip Basic storage unit is normally a cell one bit per cell Mul0ple RAM chips form a memory StaAc RAM SRAM Each cell stores a bit with a four or six transistor circuit Retains value inde nitely as long as it is kept powered Rela0vely insensi0ve to electrical noise EMI radia0on etc Faster and more expensive than DRAM Dynamic RAM DRAM Each cell stores bit with a capacitor One transistor is used for access Value must be refreshed every 10 100 ms More sensi0ve to disturbances EMI radia0on than SRAM Slower and cheaper than SRAM 3 Carnegie Mellon SRAM vs DRAM Summary Trans per bit Access Needs Needs time refresh EDC Cost Applications SRAM 4 or 6 1X No Maybe 100x Cache memories DRAM 1 10X Yes Yes 1X Main memories frame buffers 4 Carnegie Mellon ConvenAonal DRAM OrganizaAon d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip 0 2 bits to from CPU 2 rows 1 supercell 2 1 2 8 bits 3 0 addr Memory controller 1 cols 3 data Internal row buffer 5 Carnegie Mellon Reading DRAM Supercell 2 1 16 x 8 DRAM chip 0 RAS 2 2 2 3 0 addr Rows Memory controller 1 Cols 1 2 8 3 data Internal row buffer 6 Carnegie Mellon Reading DRAM Supercell 2 1 16 x 8 DRAM chip 0 CAS 1 2 Rows Memory controller supercell 2 1 2 3 0 addr To CPU 1 Cols 1 2 8 3 data supercell 2 1 Internal row buffer 7 Carnegie Mellon Memory Modules addr row i col j supercell i j DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs DRAM 7 bits bits 56 63 48 55 63 56 55 48 47 bits 40 47 40 39 bits 32 39 bits 24 31 bits 16 23 32 31 24 23 16 15 bits 8 15 bits 0 7 8 7 64 bit doubleword at main memory address A 0 Memory controller 64 bit doubleword 8 Carnegie Mellon Enhanced DRAMs Basic DRAM cell has not changed since its invenAon in 1966 Commercialized by Intel in 1970 DRAM cores with beRer interface logic and faster I O Synchronous DRAM SDRAM Uses a conven0onal clock signal instead of asynchronous control Allows reuse of the row addresses e g RAS CAS CAS CAS Double data rate synchronous DRAM DDR SDRAM Double edge clocking sends two bits per cycle per pin Di erent types dis0nguished by size of small prefetch bu er DDR 2 bits DDR2 4 bits DDR4 8 bits By 2010 standard for most server and desktop systems Intel Core i7 supports only DDR3 SDRAM 9 Carnegie Mellon NonvolaAle Memories DRAM and SRAM are volaAle memories Lose informa0on if powered o NonvolaAle memories retain value even if powered o Read only memory ROM programmed during produc0on Programmable ROM PROM can be programmed once Eraseable PROM EPROM can be bulk erased UV X Ray Electrically eraseable PROM EEPROM electronic erase capability Flash memory EEPROMs with par0al sector erase capability Wears out aaer about 100 000 erasings Uses for NonvolaAle Memories Firmware programs stored in a ROM BIOS controllers for disks network cards graphics accelerators security subsystems Solid state disks replace rota0ng disks in thumb drives smart phones mp3 players tablets laptops Disk caches 10 Carnegie Mellon TradiAonal Bus Structure ConnecAng CPU and Memory A bus is a collecAon of parallel wires that carry address data and control signals Buses are typically shared by mulAple devices CPU chip Register file ALU System bus Bus interface I O bridge Memory bus Main memory 11 Carnegie Mellon Memory Read TransacAon 1 CPU places address A on the memory bus Register file eax Load operation movl A eax ALU I O bridge Bus interface Main memory A x 0 A 12 Carnegie Mellon Memory Read TransacAon 2 Main memory reads A from the memory bus retrieves word x and places it on the bus Register file eax Load operation movl A eax ALU Main memory I O bridge Bus interface x x 0 A 13 Carnegie Mellon Memory Read TransacAon 3 CPU read word x from the bus and copies it into register eax Register file eax x Load operation movl A eax ALU I O bridge Bus interface Main memory x 0 A 14 Carnegie Mellon Memory Write TransacAon 1 CPU places address A on bus Main memory reads it and waits for the corresponding data word to arrive Register file eax y Store operation movl eax A ALU I O bridge Bus interface A Main memory 0 A 15 Carnegie Mellon Memory Write TransacAon 2 CPU places data word y on the bus Register file eax y Store operation movl eax A ALU Main memory I O bridge Bus interface y 0 A 16 Carnegie Mellon Memory Write TransacAon 3 Main memory reads data word y from the bus and stores it at address A register file eax y Store operation movl eax A ALU main memory 0 I O bridge bus interface y A 17 Carnegie Mellon What s Inside A Disk Drive Arm Spindle Platters Actuator SCSI connector Electronics including a processor and memory Image courtesy of Seagate Technology 18 Carnegie Mellon Disk Geometry Disks consist of plaRers each with two surfaces Each surface consists of concentric rings called tracks Each track consists of sectors separated by gaps Tracks Surface Track k Gaps Spindle Sectors 19 Carnegie Mellon Disk Geometry Muliple PlaRer View Aligned tracks form a cylinder Cylinder k Surface 0 Platter 0 Surface 1 Surface 2 Platter 1 Surface 3 Surface 4 Platter 2 Surface 5 Spindle 20 Carnegie Mellon Disk Capacity Capacity maximum number of bits that can be stored Vendors express capacity in units of gigabytes GB where 1 GB 109 Bytes Lawsuit pending Claims decep0ve adver0sing Capacity is determined by these technology factors Recording density bits in number of bits that can be squeezed into a 1 inch segment of a track Track density tracks in number of tracks that can be squeezed into a 1 inch radial segment Areal density bits in2 product of recording and track density Modern disks parAAon tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors determined by the circumference of innermost track Each zone has a di erent number of sectors track 21 Carnegie Mellon CompuAng Disk Capacity Capacity bytes sector x avg sectors track x tracks surface x surfaces plaRer x plaRers disk Example 512 bytes sector 300 sectors track on average 20 000 tracks surface 2 surfaces plaher 5 plahers disk Capacity 512 x 300 x 20000 x 2 x 5 30 720 000 000 30 72 GB 22 Carnegie Mellon Disk OperaAon Single PlaRer View The disk surface spins at a fixed
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