Student Number University of Toronto Faculty of Applied Science and Engineering Test 2 April 2004 ECE532S Digital Hardware Examiner Paul Chow 1 There are 5 questions and 10 pages Do all questions The total number of marks is 50 The duration of the test is 50 minutes 2 ALL WORK IS TO BE DONE ON THESE SHEETS Use the back of the pages if you need more space Be sure to indicate clearly if your work continues elsewhere 3 No calculators or other computing devices allowed 4 Closed book No aids permitted 1 10 2 10 3 10 4 10 5 10 Total 50 Page 1 of 10 1 Starting with some short answer questions 2 marks a Define setup and hold time for a flip flop 2 marks b What happens when a flip flop goes metastable and how long will it stay in that state 2 marks c What is a clock domain 2 marks d Why is flip chip bonding preferred for high speed packaging 2 marks e What is jitter in the context of timing analysis Page 2 of 10 10 marks 2 Using a figure describe how a basic MicroBlaze system is implemented For each of the following components or functions you must show where in FPGA on board in PC etc and how they are implemented FPGA logic external chip etc Also show how all the pieces are connected MicroBlaze processor UART Ethernet physical layer interface PHY instruction and data memory using on chip memory Ethernet controller instruction and data memory using off chip memory serial port RS232 physical drivers FPGA download functions XMD stub gcc Page 3 of 10 3 Consider the circuit shown below D 50MHz Clock Comb Logic 4ns Q D Q 350ps From the data sheets you have also gathered the following information about the flip flops setup hold ClockToQ The clock tree has a maximum skew of behind the other by The clock source is a 50 MHz clock or 5 marks i e the phase of any one branch could be ahead or period with a jitter of accounting for the combinational logic and the wire delay for the data a There is a delay of travelling between the two flip flops Being a very conservative designer you also like to add of timing margin to all of your calculations Determine whether the circuit will operate correctly assuming that you include your own timing margin by checking the setup and hold times for the receiving flip flop in the above circuit Page 4 of 10 Question 3 a continued Page 5 of 10 5 marks b You also know of a similar circuit in another part of your design except that it does not have the combinational logic The output of the first flip flop connects directly to the input of the second flip flop Assuming that the routing delay is determine whether this circuit meets timing Page 6 of 10 4 You have inherited the anti lock braking system module for a car as the next task in your job There have been numerous reports of the system not working properly The circuit capturing the data from the shaft encoder to calculate the speed is shown below 16 bit Binary Counter 16 bit Reg Shaft Encoder 100 MHz Logic 16 16 Enable 100 MHz The shaft encoder generates 1000 pulses per revolution The pulses are counted in the 16 bit binary counter The value of the counter is periodically sampled in the 100MHz domain when the Enable signal goes high The sampling period is frequent enough that the 16 bit counter has adequate range 5 marks a Why is this circuit unreliable Give an example of how it could fail Page 7 of 10 Question 4 continued 5 marks b How would you fix this circuit You are free to start over with a new design except that the same shaft encoder is to be used and the core logic should run at 100MHz Page 8 of 10 5 You have just joined a new company as the team leader of the ASIC verification group After a number of weeks of hiring you are now meeting your team of young recruits who are fresh out of school 3 marks a What will you tell your team about the importance of simulation in the overall ASIC design flow 3 marks b Your team has just grown to add some people that will be responsible for verifying a large FPGA What will you tell them about the differences between designing ASICs and FPGAs Page 9 of 10 4 marks c One of the new recruits says that simulation is a waste of time for FPGAs What is your response Page 10 of 10
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