11Electrical and Computer EngineeringCPE/EE 422/522 Chapter 1 - Review of Logic Design FundamentalsDr. Rhonda Kay GaedeUAHElectrical and Computer EngineeringPage 2 of 77UAH CPE/EE 422/522Chapter 1• Combinational Logic has no control inputs. When the inputs to a combinational network change, the output changes ____________________________.1.1 Combinational Logicx1x2xnz1z2zmX = x1x2... xnZ = z1z2... zm2Electrical and Computer EngineeringPage 3 of 77UAH CPE/EE 422/522Chapter 11.1 Combinational Logic -Basic Logic GatesElectrical and Computer EngineeringPage 4 of 77UAH CPE/EE 422/522Chapter 11.1 Combinational Logic -Full Adder (Minterm Form)ModuleTruth tableX Y Cin Cout Sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1m-formSum =Cout = Sum =Cout =3Electrical and Computer EngineeringPage 5 of 77UAH CPE/EE 422/522Chapter 11.1 Combinational Logic -Full Adder (Maxterm Form)ModuleTruth tableX Y Cin Cout Sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1Sum =Sum = Cout =Cout =m-formSum = Cout = Electrical and Computer EngineeringPage 6 of 77UAH CPE/EE 422/522Chapter 11.2 Boolean Algebra and Algebraic Simplification• Some routines are widely used and been pooled into subroutine libraries.• Operating systems are programs that manage the resources of a computer for the benefit of the programs that run on that machine• Software Categories– Systems - OS, compilers, assemblers, etc.– Applications - spreadsheets, text editors, etc.4Electrical and Computer EngineeringPage 7 of 77UAH CPE/EE 422/522Chapter 11.3 More Boolean Algebra and Algebraic SimplificationElectrical and Computer EngineeringPage 8 of 77UAH CPE/EE 422/522Chapter 11.2 Boolean Algebra with Exclusive ORX0X =⊕'X1X =⊕0XX =⊕1'XX =⊕XYYX ⊕=⊕(Commutative law))ZY(XZ)YX(⊕⊕=⊕⊕XZXY)ZY(X ⊕=⊕(Distributive law)'Y'XXYY'X'YX)'YX(+=⊕=⊕=⊕5Electrical and Computer EngineeringPage 9 of 77UAH CPE/EE 422/522Chapter 11.3 Karnaugh Maps• Convenient way to simplify logic functions of 3, 4, 5, (6) variables• Four-variable K-map– Each square ____________________________• 1 ________________________________ • 0______________________________ • d ____________________________– ------------------------------------------– --------------------------------------– adjacent cells ____________________________Electrical and Computer EngineeringPage 10 of 77UAH CPE/EE 422/522Chapter 11.3 Karnaugh Maps - ExamplesADCBADCB6Electrical and Computer EngineeringPage 11 of 77UAH CPE/EE 422/522Chapter 11.3 Karnaugh Maps - Sum of Products• Function consists of a sum of _________________• Prime implicant____________________________________________________________________________________________• Prime implicant is ______________ if it contains a 1 that is not contained in any other prime implicantElectrical and Computer EngineeringPage 12 of 77UAH CPE/EE 422/522Chapter 11.3 Karnaugh Maps -Prime Implicant Selection• Two minimum formsf =f =ADCB7Electrical and Computer EngineeringPage 13 of 77UAH CPE/EE 422/522Chapter 11.3 Karnaugh Maps -Selection Procedure1. Choose a 1 (_______) that has not been covered yet2. Find all _s and __s adjacent to that minterm. (Check the n adjacent squares on an n-variable map.)3. If a single term covers the minterm and all the adjacent 1s and ds, then that term is an ________ prime implicant, so select that term.4. Repeat steps 1, 2, 3 until all essential primeimplicants have been chosen5. Find a ________ set of prime implicants that cover the remaining 1s on the map. If there is more than one such set, choose a set with a ______________ ______________Electrical and Computer EngineeringPage 14 of 77UAH CPE/EE 422/522Chapter 11.4 Designing with NANDand NOR Gates• Implementation of NAND and NOR gates is easier than that of AND and OR gates (e.g., CMOS)8Electrical and Computer EngineeringPage 15 of 77UAH CPE/EE 422/522Chapter 11.4 Designing with NANDand NOR Gates (continued)• Any logic function can be realized using only NAND or NOR gates -___________________________________ –1:–0: –a’:– ab: –a+b:Electrical and Computer EngineeringPage 16 of 77UAH CPE/EE 422/522Chapter 11.4 Designing with NAND and NOR Gates -Conversion to NOR Gates• Start with POS (_____________)– circle 0s in K-maps• Find network of OR and AND gates9Electrical and Computer EngineeringPage 17 of 77UAH CPE/EE 422/522Chapter 11.4 Designing with NANDand NOR Gates -Conversion to NAND Gates• Start with SOP (Sum of Products)– circle 1s in K-maps• Find network of OR and AND gatesElectrical and Computer EngineeringPage 18 of 77UAH CPE/EE 422/522Chapter 11.13 Tristate Logic and Busses•Four kinds of tristate buffersB is a control input used to enable and disable the output10Electrical and Computer EngineeringPage 19 of 77UAH CPE/EE 422/522Chapter 11.13 Tristate Logic and Busses -Data TransferElectrical and Computer EngineeringPage 20 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches –Sequential Networks• Have memory (state)– Present state depends not only on the ______________, but also on all previous inputs (history)– Future state depends on the ___________ and _______))t(Q),t(X(F)t(Z =))t(Q),t(X(G)t(Q =+Flip-flops are commonly used as storage devices:D-FF, JK-FF, T-FFx1x2xnz1z2zmQ11Electrical and Computer EngineeringPage 21 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches - Clocked D Flip-Flop with Rising-edge TriggerNext stateThe next state in response to the ________ of the clock is equal to the ______ input before the rising edgeElectrical and Computer EngineeringPage 22 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches –Clocked JK Flip-FlopNext stateJK = 00 =>JK = 10 =>JK = 01 => JK = 11 =>12Electrical and Computer EngineeringPage 23 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches –Clocked T Flip-FlopNext stateT = 1 => T = 0 =>Electrical and Computer EngineeringPage 24 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches –S-R Latch13Electrical and Computer EngineeringPage 25 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches –Transparent D LatchElectrical and Computer EngineeringPage 26 of 77UAH CPE/EE 422/522Chapter 11.6 Flip-Flops and Latches –Transparent D Latch14Electrical and Computer EngineeringPage 27 of 77UAH CPE/EE 422/522Chapter 11.7 Mealy Sequential