•1CPE/EE 422/522Advanced Logic DesignL07Electrical and Computer EngineeringUniversity of Alabama in Huntsville18/06/2003 UAH-CPE/EE 422/522 AM 2Outline• What we know– How to model Combinational Networks in VHDL• Structural, Dataflow, Behavioral– How to model Flip-flops in VHDL– Processes– Delays (delta, transport, inertial)• What we do not know– How to model FSM in VHDL– Wait statements– Variables, Signals, Arrays– VHDL Operators– Procedures, Functions– Packages, Libraries– Additional Topics (if time)18/06/2003 UAH-CPE/EE 422/522 AM 3Review: VHDL Program Structure18/06/2003 UAH-CPE/EE 422/522 AM 4Review: JK Flip-Flop Model18/06/2003 UAH-CPE/EE 422/522 AM 5Review: VHDL Models for a MUXSel represents the integerequivalent of a 2-bit binary number with bits A and BIf a MUX model is used inside a process, the MUX can be modeled using a CASE statement(cannot use a concurrent statement):18/06/2003 UAH-CPE/EE 422/522 AM 6Timing Model• VHDL uses the following simulation cycle to model the stimulus and response nature of digital hardwareDelayStart SimulationUpdate Signals Execute ProcessesEnd Simulation•218/06/2003 UAH-CPE/EE 422/522 AM 7Review: Delay Types• All VHDL signal assignment statements prescribe an amount of time that must transpire before the signal assumes its new value• This prescribed delay can be in one of three forms:– Transport -- prescribes propagation delay only– Inertial -- prescribes propagation delay and minimum input pulse width– Delta -- the default if no delay time is explicitly specifiedInputdelayOutput18/06/2003 UAH-CPE/EE 422/522 AM 8Problem #1• Using the labels, list the order in which the following signal assignments are evaluated if in2 changes from a '0' to a '1'. Assume in1 has been a '1' and in2 has been a '0' for a long time, and then at time t in2 changes from a '0' to a '1'.entity not_another_prob isport (in1, in2: in bit;a: out bit);end not_another_prob;architecture oh_behave of not_another_prob issignal b, c, d, e, f: bit;beginL1: d <= not(in1);L2: c<= not(in2);L3: f <= (d and in2) ; L4: e <= (c and in1) ;L5: a <= not b;L6: b <= e or f;end oh_behave;18/06/2003 UAH-CPE/EE 422/522 AM 9Modeling a Sequential MachineMealy Machine for 8421 BCD to 8421 BCD + 3 bit serial converterHow to model this in VHDL?18/06/2003 UAH-CPE/EE 422/522 AM 10Behavioral VHDL ModelTwo processes: • the first represents the combinational network;• the second represents the state register18/06/2003 UAH-CPE/EE 422/522 AM 11Simulation of the VHDL ModelSimulation command file:Waveforms:18/06/2003 UAH-CPE/EE 422/522 AM 12Dataflow VHDL Model33213132131221''''''')()()(XQQXZQQXQQXQQQtQQtQQtQ+=++===+++•318/06/2003 UAH-CPE/EE 422/522 AM 13Structural ModelPackage bit_pack is a part of library BITLIB –includes gates, flip-flops, counters(See Appendix B for details)18/06/2003 UAH-CPE/EE 422/522 AM 14Simulation of the Structural ModelSimulation command file:Waveforms:18/06/2003 UAH-CPE/EE 422/522 AM 15Wait Statements• ... an alternative to a sensitivity list– Note: a process cannot have both wait statement(s)and a sensitivity list• Generic form of a process with wait statement(s)processbeginsequential -statementswait statementsequential -statementswait-statement...end process;How wait statements work?• Execute seq. statement until a wait statement is encountered.• Wait until the specified condition is satisfied.• Then execute the next set of sequential statements until the next wait statement is encountered.• ...• When the end of the process is reached start over again at the beginning.18/06/2003 UAH-CPE/EE 422/522 AM 16Forms of Wait Statements• Wait on – until one of the signals in the sensitivity list changes• Wait for– waits until the time specified by the time expression has elapsed– What is this:wait for 0 ns;• Wait until– the booleanexpression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUEwait on sensitivity-list;wait for time-expression;wait until boolean -expression;18/06/2003 UAH-CPE/EE 422/522 AM 17Using Wait Statements (1)18/06/2003 UAH-CPE/EE 422/522 AM 18Using Wait Statements (2)•418/06/2003 UAH-CPE/EE 422/522 AM 19Variables• What are they for: Local storage in processes, procedures, and functions• Declaring variablesvariable list_of_variable_names : type_name [ := initial value ];• Variables must be declared within the process in which they are used and are local to the process– Note: exception to this is SHARED variables18/06/2003 UAH-CPE/EE 422/522 AM 20Signals• Signals must be declared outside a process• Declaration formsignal list_of_signal_names : type_name [ := initial value ];• Declared in an architecture can be used anywhere within that architecture18/06/2003 UAH-CPE/EE 422/522 AM 21Constants• Declaration formconstant constant_name : type_name := constant_value;• Constants declared at the start of an architecturecan be used anywhere within that architecture• Constants declared within a process are localto that processconstant delay1 : time := 5 ns;18/06/2003 UAH-CPE/EE 422/522 AM 22Variables vs. Signals• Variable assignment statementvariable_name := expression;• Signal assignment statementsignal_name <= expression [after delay];– expression is evaluated and the variable is instantaneously updated(no delay, not even delta delay)– expression is evaluated and the signal is scheduled to change after delay; if no delay is specified the signal is scheduled to be updated after a delta delay18/06/2003 UAH-CPE/EE 422/522 AM 23Variables vs. Signals (cont’d)Process Using Variables Process Using SignalsSum = ?Sum = ?18/06/2003 UAH-CPE/EE 422/522 AM 24Predefined VHDL Types• Variables, signals, and constants can have any one of the predefined VHDL types or they can have a user-defined type• Predefined Types– bit – {‘0’, ‘1’}– boolean – {TRUE, FALSE}– integer – [-231- 1.. 231– 1}– real – floating point number in range –1.0E38 to +1.0E38– character – legal VHDL characters including lower-uppercase letters, digits, special characters, ...– time – an integer with units fs, ps, ns, us, ms, sec, min, or hr•518/06/2003 UAH-CPE/EE 422/522 AM 25User Defined Type• Common user-defined type is enumeratedtype state_type is (S0, S1, S2, S3, S4, S5); signal state :
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