11Electrical and Computer EngineeringCPE/EE 422/522 Chapter 5 - Digital Design with SM ChartsDr. Rhonda Kay GaedeUAHElectrical and Computer EngineeringPage 2 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts• State graphs used to describe state machines controlling a digital system• Alternative: use state machine flowchart2Electrical and Computer EngineeringPage 3 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts• SM chart or ASM (Algorithmic State Machine) chart• Easier to understand the operation of digital system by examination of the SM chart instead of equivalent state graph• SM chart leads directly to hardware realizationElectrical and Computer EngineeringPage 4 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts -Components3Electrical and Computer EngineeringPage 5 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts - SM BlocksSM chart is constructed from SM blocksState S1 is entered => Z1 and Z2 become 1if X1=0 Z3 and Z4 become 1if X1=1 and X3=0 Z5 become 1Electrical and Computer EngineeringPage 6 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts -Equivalent SM Blocks4Electrical and Computer EngineeringPage 7 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts - Equivalent SM Charts for Combinational NetworksElectrical and Computer EngineeringPage 8 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts -Block with Feedback5Electrical and Computer EngineeringPage 9 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts -Equivalent SM BlocksElectrical and Computer EngineeringPage 10 of 25UAH CPE/EE 422/522Chapter 55.1 State Machine Charts - Converting a State Graph to an SM Chart6Electrical and Computer EngineeringPage 11 of 25UAH CPE/EE 422/522Chapter 55.2 Derivation of SM Charts -SM Chart for Binary MultiplierElectrical and Computer EngineeringPage 12 of 25UAH CPE/EE 422/522Chapter 55.2 Derivation of SM Charts -VHDL for Binary Multiplierentity Mult isport(CLK,St,K,M: in bit;Load,Sh,Ad,Done: out bit);end mult;architecture SMbehave of Mult issignal State, Nextstate: integer range 0 to 3;beginprocess(St, K, M, State) -- start if state or inputs changebeginLoad <= '0'; Sh <= '0'; Ad <= '0';case State iswhen 0 => if St = '1' then -- St (state 0)Load <= '1';Nextstate <= 1;else Nextstate <= 0; -- St'end if;7Electrical and Computer EngineeringPage 13 of 25UAH CPE/EE 422/522Chapter 55.2 Derivation of SM Charts -VHDL for Binary Multiplier (continued)when 1 => if M = '1' then -- M (state 1)Ad <= '1';Nextstate <= 2;else -- M'Sh <= '1';if K = '1' then Nextstate <= 3; -- Kelse Nextstate <= 1; -- K'end if;end if;when 2 => Sh <= '1'; -- (state 2)if K = '1' then Nextstate <= 3; -- Kelse Nextstate <= 1; -- K'end if;when 3 => Done <= '1'; -- (state 3)Nextstate <= 0;end case;end process;Electrical and Computer EngineeringPage 14 of 25UAH CPE/EE 422/522Chapter 55.2 Derivation of SM Charts -VHDL for Binary Multiplier (concluded)process(CLK)begin if CLK = '1' thenState <= Nextstate; -- update state on rising edgeend if;end process;end SMbehave;8Electrical and Computer EngineeringPage 15 of 25UAH CPE/EE 422/522Chapter 55.2 Derivation of SM Charts -Electronic Dice Game• Two counters are used to simulate the roll of the dice• Rules of the game– After the first roll of the dice, the player wins if the sum is 7 or 11. The player loses if the sum is 2, 3, or 12. Otherwise, the sum the player obtained on the first roll is referred to as a point, and he or she must roll the dice again.– On the second or subsequent roll of the dice, the player wins if the sum equals the point, and he or she loses if the sum is 7. Otherwise, the player must roll again until he or she finallywins or loses.Electrical and Computer EngineeringPage 16 of 25UAH CPE/EE 422/522Chapter 5Electronic Dice Game Block DiagramElectronic Dice Game Block Diagram9Electrical and Computer EngineeringPage 17 of 25UAH CPE/EE 422/522Chapter 5Electronic Dice Game FlowchartElectronic Dice Game FlowchartElectrical and Computer EngineeringPage 18 of 25UAH CPE/EE 422/522Chapter 5Electronic Dice Game Electronic Dice Game Inputs and OutputsInputs and Outputs• Inputs–D7 -– D711 -– D2312 -–Eq -–Rb -–Reset -• Outputs–Roll -–Sp -–Win -– Lose -10Electrical and Computer EngineeringPage 19 of 25UAH CPE/EE 422/522Chapter 5Electronic Dice Game SMElectronic Dice Game SMElectrical and Computer EngineeringPage 20 of 25UAH CPE/EE 422/522Chapter 5Electronic Dice Game Electronic Dice Game Behavioral VHDL ModelBehavioral VHDL Modelentity DiceGame is port (Rb, Reset, CLK: in bit;Sum: in integer range 2 to 12;Roll, Win, Lose: out bit);end DiceGame;architecture DiceBehave of DiceGame issignal State, Nextstate: integer range 0 to 5; signal Point: integer range 2 to 12;signal Sp: bit;beginprocess(Rb, Reset, Sum, State)beginSp <= '0'; Roll <= '0'; Win <= '0'; Lose <= '0';case State iswhen 0 => if Rb = '1' then Nextstate <= 1; end if;when 1 => if Rb = '1' then Roll <= '1';elsif Sum = 7 or Sum = 11 then Nextstate <= 2;elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3;else Sp <= '1'; Nextstate <= 4;end if;when 2 => Win <= '1';if Reset = '1' then Nextstate <= 0; end if;11Electrical and Computer EngineeringPage 21 of 25UAH CPE/EE 422/522Chapter 5Electronic Dice GameElectronic Dice GameBehavioral VHDL ModelBehavioral VHDL Modelwhen 3 => Lose <= '1';if Reset = '1' then Nextstate <= 0; end if;when 4 => if Rb = '1' then Nextstate <= 5; end if;when 5 =>if Rb = '1' then Roll <= '1';elsif Sum = Point then Nextstate <= 2;elsif Sum = 7 then Nextstate <= 3;else Nextstate <= 4;end if; end case;end process;process(CLK)beginif rising_edge(CLK) thenState <= Nextstate;if Sp = '1' then Point <= Sum; end if;end if;end process;end DiceBehave;Electrical and Computer EngineeringPage 22 of 25UAH CPE/EE 422/522Chapter 5Dice Game Test Dice Game Test --SM ChartSM Chart12Electrical and Computer EngineeringPage 23 of 25UAH CPE/EE 422/522Chapter 5Dice Game Test Module VHDLDice Game Test Module VHDLentity GameTest isport(Rb, Reset: out bit;Sum: out integer range 2 to 12;CLK: inout bit;Roll, Win, Lose: in bit);end GameTest;architecture dicetest of GameTest issignal Tstate, Tnext: integer range 0 to 3; signal Trig1: bit;type arr is array(0 to 11) of integer;constant Sumarray:arr := (7,11,2,4,7,5,6,7,6,8,9,6);beginCLK <= not CLK after 20 ns;process(Roll, Win, Lose, Tstate)variable i: natural; -- i is initialized to 0begincase Tstate iswhen 0 => Rb <= '1'; Reset <='0';if i>=12 then Tnext <= 3;elsif Roll = '1' then