•1CPE/EE 422/522Advanced Logic DesignL06Electrical and Computer EngineeringUniversity of Alabama in Huntsville13/06/2003 UAH-CPE/EE 422/522 AM 2Outline• What we know– Combinational Networks– Sequential Networks: • Basic Building Blocks, Mealy & Moore Machines, Max Frequency, Setup & Hold Times, Synchronous Design• What we do not know– Equivalent states and reduction of state tables– Hardware Description Languages13/06/2003 UAH-CPE/EE 422/522 AM 3Intro to VHDL• Technology trends– 1 billion transistor chip running at 20 GHz in 2007• Need for Hardware Description Languages– Systems become more complex– Design at the gate and flip-flop level becomes very tedious and time consuming• HDLs allow– Design and debugging at a higher level before conversion to the gate and flip-flop level– Tools for synthesis do the conversion• VHDL, Verilog• VHDL – VHSIC Hardware Description Language13/06/2003 UAH-CPE/EE 422/522 AM 4Intro to VHDL• Developed originally by DARPA– for specifying digital systems • International IEEE standard (IEEE 1076-1993)• Hardware Description, Simulation, Synthesis• Provides a mechanism for digital design and reusable design documentation• Support different description levels– Structural (specifying interconnections of the gates), – Dataflow (specifying logic equations), and – Behavioral (specifying behavior)• Top-down, Technology Dependent13/06/2003 UAH-CPE/EE 422/522 AM 5VHDL Description of Combinational Networks13/06/2003 UAH-CPE/EE 422/522 AM 6Entity-Architecture PairFull Adder Example•213/06/2003 UAH-CPE/EE 422/522 AM 7VHDL Program Structure13/06/2003 UAH-CPE/EE 422/522 AM 84-bit Adder13/06/2003 UAH-CPE/EE 422/522 AM 94-bit Adder (cont’d)13/06/2003 UAH-CPE/EE 422/522 AM 104-bit Adder - Simulation13/06/2003 UAH-CPE/EE 422/522 AM 11Modeling Flip-Flops Using VHDL Processes• Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time General form of process13/06/2003 UAH-CPE/EE 422/522 AM 12Concurrent Statements vs. ProcessSimulation ResultsA, B, C, D are integersA=1, B=2, C=3, D=0D changes to 4 at time 10time delta A B C D0 +0 0 1 2 010 +0 1 2 3 4 (stat. 3 exe.)10 +1 1 2 4 4 (stat. 2 exe.)10 +2 1 4 4 4 (stat. 1 exe.)10 +3 4 4 4 4 (no exec.)•313/06/2003 UAH-CPE/EE 422/522 AM 13D Flip-flop ModelBit values are enclosed in single quotes13/06/2003 UAH-CPE/EE 422/522 AM 14JK Flip-Flop Model13/06/2003 UAH-CPE/EE 422/522 AM 15JK Flip-Flop Model13/06/2003 UAH-CPE/EE 422/522 AM 16Using Nested IFsand ELSEIFs13/06/2003 UAH-CPE/EE 422/522 AM 17VHDL Models for a MUXSel represents the integerequivalent of a 2-bit binary number with bits A and BIf a MUX model is used inside a process, the MUX can be modeled using a CASE statement(cannot use a concurrent statement):13/06/2003 UAH-CPE/EE 422/522 AM 18MUX Models (1)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR isport (A : in std_logic_vector(15 downto 0);SEL : in std_logic_vector( 3 downto 0);Y : out std_logic);end SELECTOR;architecture RTL1 of SELECTOR isbeginp0 : process (A, SEL)beginif (SEL = "0000") then Y <= A(0);elsif (SEL = "0001") then Y <= A(1);elsif (SEL = "0010") then Y <= A(2);elsif (SEL = "0011") then Y <= A(3);elsif (SEL = "0100") then Y <= A(4);elsif (SEL = "0101") then Y <= A(5);elsif (SEL = "0110") then Y <= A(6);elsif (SEL = "0111") then Y <= A(7);elsif (SEL = "1000") then Y <= A(8);elsif (SEL = "1001") then Y <= A(9);elsif (SEL = "1010") then Y <= A(10);elsif (SEL = "1011") then Y <= A(11);elsif (SEL = "1100") then Y <= A(12);elsif (SEL = "1101") then Y <= A(13);elsif (SEL = "1110") then Y <= A(14);else Y <= A(15);end if;end process;end RTL1;•413/06/2003 UAH-CPE/EE 422/522 AM 19MUX Models (2)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR isport (A : in std_logic_vector(15 downto 0);SEL : in std_logic_vector( 3 downto 0);Y : out std_logic);end SELECTOR;architecture RTL3 of SELECTOR isbeginwith SEL selectY <= A(0) when "0000", A(1) when "0001", A(2) when "0010", A(3) when "0011", A(4) when "0100", A(5) when "0101", A(6) when "0110", A(7) when "0111", A(8) when "1000", A(9) when "1001", A(10) when "1010", A(11) when "1011", A(12) when "1100", A(13) when "1101", A(14) when "1110", A(15) when others; end RTL3;13/06/2003 UAH-CPE/EE 422/522 AM 20MUX Models (3)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR isport (A : in std_logic_vector(15 downto 0);SEL : in std_logic_vector( 3 downto 0);Y : out std_logic);end SELECTOR;architecture RTL2 of SELECTOR isbeginp1 : process (A, SEL)begincase SEL iswhen "0000" => Y <= A(0);when "0001" => Y <= A(1);when "0010" => Y <= A(2);when "0011" => Y <= A(3);when "0100" => Y <= A(4);when "0101" => Y <= A(5);when "0110" => Y <= A(6);when "0111" => Y <= A(7);when "1000" => Y <= A(8);when "1001" => Y <= A(9);when "1010" => Y <= A(10);when "1011" => Y <= A(11);when "1100" => Y <= A(12);when "1101" => Y <= A(13);when "1110" => Y <= A(14);when others => Y <= A(15);end case;end process;end RTL2;13/06/2003 UAH-CPE/EE 422/522 AM 21MUX Models (4)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR isport (A : in std_logic_vector(15 downto 0);SEL : in std_logic_vector( 3 downto 0);Y : out std_logic);end SELECTOR;architecture RTL4 of SELECTOR isbeginY <= A( conv_integer(SEL));end RTL4;13/06/2003 UAH-CPE/EE 422/522 AM 22Compilation and Simulation of VHDL Code• Compiler (Analyzer) – checks the VHDL source code – does it conforms with VHDL syntax and semantic rules– are references to libraries correct• Intermediate form used by a simulator or by a synthesizer• Elaboration– create ports, allocate memory storage, create interconnections, ... – establish mechanism for executing of VHDL processes13/06/2003 UAH-CPE/EE 422/522 AM 23Timing Model• VHDL uses the following simulation cycle to model the stimulus and response nature of digital hardwareDelayStart SimulationUpdate Signals Execute ProcessesEnd Simulation13/06/2003 UAH-CPE/EE 422/522 AM 24Delay Types• All VHDL signal assignment statements prescribe an amount of time that must
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