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11Electrical and Computer EngineeringCPE/EE 422/522 Chapter 8 - Additional Topics in VHDLDr. Rhonda Kay GaedeUAHElectrical and Computer EngineeringPage 2 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Signal Attributes that return a valueA’event – true if a ______________ has just occurredA’active – true if A has ____________________, even if A does not change2Electrical and Computer EngineeringPage 3 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Signal Attribute Evaluation Example• Event– occurs on a signal every time it is ___________• Transaction– occurs on a signal every time it is ____________•Example:A <= B - - B changes at time TA’eventT + 1dTB’eventSignal AttributesElectrical and Computer EngineeringPage 4 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Signal Attributesthat create a signal3Electrical and Computer EngineeringPage 5 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Attribute Test VHDL and WaveformsElectrical and Computer EngineeringPage 6 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Using Attributes for Error Checkingcheck: processbeginwait until rising_edge(Clk);assert (D’stable(setup_time))report(“Setup time violation”)severity error;wait for hold_time;assert (D’stable(hold_time))report(“Hold time violation”)severity error;end process check;4Electrical and Computer EngineeringPage 7 of 54 UAH CPE/EE 422/522Chapter 8Assert Statement• If boolean expression is ______display the string expression on the monitor• Severity levels: ________, __________, ________, __________assert boolean-expressionreport string-expressionseverity severity-levelElectrical and Computer EngineeringPage 8 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Array AttributesA can be either an ___________ or an ___________.Array attributes workwith _______, _______, and _______.5Electrical and Computer EngineeringPage 9 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Procedure for Adding Vectors without Using AttributesNote: Add1 and Add2 vectors must be dimensioned as N-1 downto 0.Use ___________ to write more general procedure that places no restrictions on the range of vectors other than the ________ must be the same.Electrical and Computer EngineeringPage 10 of 54 UAH CPE/EE 422/522Chapter 88.1 Attributes - Procedure for Adding Vectors with Using Attributes6Electrical and Computer EngineeringPage 11 of 54 UAH CPE/EE 422/522Chapter 88.2 Transport and Inertial DelaysReject is equivalent to a combination of inertial and transport delay:Zm <= X after 4 ns;Z3 <= transport Zm after 6 ns; Electrical and Computer EngineeringPage 12 of 54 UAH CPE/EE 422/522Chapter 88.3 Operator Overloading• Operators +, - operate on integers • Write procedures for bit vector addition/subtraction– addvec, subvec• Operator overloading allows using + operator to implicitly call an appropriate addition function• How does it work?– When compiler encounters a function declaration in which the function name is an operator enclosed in double quotes, the compiler treats the function as an operator overloading (“+”)– when a “+” operator is encountered, the compiler automatically checks the types of operands and calls appropriate functions7Electrical and Computer EngineeringPage 13 of 54 UAH CPE/EE 422/522Chapter 88.3 Operator Overloading -VHDL PackageElectrical and Computer EngineeringPage 14 of 54 UAH CPE/EE 422/522Chapter 88.3 Operator Overloading - Overloading Procedures and Functions• A, B, C – bit vectors• A <= B + C + 3 ?• A <= 3 + B + C ? • Overloading can also be applied to procedures and functions– procedures have the same name –type of the actual parameters in the procedure call determines which version of the procedure is called8Electrical and Computer EngineeringPage 15 of 54 UAH CPE/EE 422/522Chapter 88.4 Multivalued Logic and Signal Resolution•Bit (0, 1)• Tristate buffers and buses =>high impedance state ‘Z’• Unknown state ‘X’– e. g., a gate is driven by ‘Z’, output is unknown– a signal is simultaneously driven by ‘0’ and ‘1’Electrical and Computer EngineeringPage 16 of 54 UAH CPE/EE 422/522Chapter 88.4 Multivalued Logic and Signal Resolution - VHDL for Tristate BuffersResolution function to determine the actual value of f since it is driven from two different sources9Electrical and Computer EngineeringPage 17 of 54 UAH CPE/EE 422/522Chapter 88.3 Multivalued Logic and Signal Resolution• VHDL signals may either be ___________ or ______________• Resolved signals have an associated ____________________• Bit type is unresolved –– there is no resolution function– if you drive a bit signal to two different values in two concurrent statements, the compiler will ____________________Electrical and Computer EngineeringPage 18 of 54 UAH CPE/EE 422/522Chapter 88.3 Multivalued Logic and Signal Resolution - Resolution Functionsignal R : X01Z := ‘Z’; ...R <= transport ‘0’ after 2 ns, ‘Z’ after 6 ns;R <= transport ‘1’ after 4 ns;R <= transport ‘1’ after 8 ns, ‘0’ after 10 ns;10Electrical and Computer EngineeringPage 19 of 54 UAH CPE/EE 422/522Chapter 88.3 Multivalued Logic and Signal Resolution - Resolution Function VHDLElectrical and Computer EngineeringPage 20 of 54 UAH CPE/EE 422/522Chapter 88.5 IEEE-1164 Standard Logic• 9-valued logic system– ‘U’ – Uninitialized– ‘X’ – Forcing Unknown– ‘0’ – Forcing 0– ‘1’ – Forcing 1– ‘Z’ – High impedance– ‘W’ – Weak unknown– ‘L’ – Weak 0–‘H’ –Weak 1– ‘-’ – Don’t careIf forcing and weak signal are tied together, the forcing signal dominates. Useful in modeling the internal operation of certain types of ICs. In this course we use a subset of the IEEE values: X10Z11Electrical and Computer EngineeringPage 21 of 54 UAH CPE/EE 422/522Chapter 88.5 IEEE-1164 Standard Logic -Resolution FunctionElectrical and Computer EngineeringPage 22 of 54 UAH CPE/EE 422/522Chapter 88.5 IEEE-1164 Standard Logic -AND Definition12Electrical and Computer EngineeringPage 23 of 54 UAH CPE/EE 422/522Chapter 88.5 IEEE-1164 Standard Logic -AND Function VHDLElectrical and Computer EngineeringPage 24 of 54 UAH CPE/EE 422/522Chapter 88.6 Generics• Used to specify ___________ for a _____________ in such a way that the ____________ values must be specified when the ____________ is instantiated • Example: rise/fall time modeling13Electrical and Computer EngineeringPage 25 of 54 UAH


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