CPE/EE 422/522 Advanced Logic Design L15OutlineFilesSlide 4Standard TEXTIO PackageReading TEXTIO fileExtracting Data from the Line BufferExtracting Data from the Line Buffer (cont’d)Writing to TEXTIO filesAn ExampleAn Example (cont’d)VHDL Code to Fill Memory ArrayVHDL Code to Fill Memory Array (cont’d)Things to RememberThings to Remember (cont’d)Networks for Arithmetic OperationsSlide 17State Graphs for Control NetworksConstraints on Input LabelsConstraints on Input Labels (cont’d)Slide 21Block Diagram of a Binary MultiplierMultiplication ExampleState Graph for Binary MultiplierBehavioral VHDL ModelBehavioral VHDL Model (cont’d)Multiplier Control with CounterMultiplier Control with Counter (cont’d)Slide 29Operation of a Multiplier Using CounterArray MultiplierArray Multiplier (cont’d)Slide 33Multiplication of Signed Binary NumbersSlide 352’s Complement MultiplierState Graph for 2’s Complement MultiplierFaster MultiplierState Graph for Faster MultiplierBehavioral Model for Faster MultiplierSlide 41Command File and SimulationTest Bench for Signed MultiplierDigital design with SM ChartsState Machine ChartsComponents of SM chartsSM BlocksEquivalent SM BlocksEquivalent SM Charts for Comb NetworksBlock with FeedbackSlide 51Converting a State Graph to an SM ChartCPE/EE 422/522Advanced Logic DesignL15Electrical and Computer EngineeringUniversity of Alabama in Huntsville14/01/19 UAH-CPE/EE 422/522 AM 2Outline•VHDL– What we know (additional topics) •Attributes•Transport and Inertial Delays•Operator Overloading•Multivalued Logic and Signal Resolution•IEEE 1164 Standard Logic•Generics•Generate Statements•Synthesis of VHDL Code•Synthesis Examples–What we don’t know•Files and Text IO–Networks for Arithmetic Operations–SM Charts14/01/19 UAH-CPE/EE 422/522 AM 3Files•File input/output in VHDL•Used in test benches–Source of test data–Storage for test results•VHDL provides a standard TEXTIO package–read/write lines of text14/01/19 UAH-CPE/EE 422/522 AM 4Files14/01/19 UAH-CPE/EE 422/522 AM 5Standard TEXTIO Package•Contains declarations and procedures for working with files composed of lines of text•Defines a file type named text:type text is file of string;•Contains procedures for reading lines of text from a file of type text and for writing lines of text to a file14/01/19 UAH-CPE/EE 422/522 AM 6Reading TEXTIO file•Readline reads a line of text and places it in a buffer with an associated pointer•Pointer to the buffer must be of type line, which is declared in the textio package as:type line is access string;•When a variable of type line is declared, it creates a pointer to a string•Codevariable buff: line;...readline (test_data, buff);–reads a line of text from test_data and places it in a buffer which is pointed to by buff14/01/19 UAH-CPE/EE 422/522 AM 7Extracting Data from the Line Buffer•To extract data from the line buffer, call a read procedure one or more times•For example, if bv4 is a bit_vector of length four, the callread(buff, bv4)–extracts a 4-bit vector from the buffer, sets bv4 equal to this vector, and adjusts the pointer buff to point to the next character in the buffer. Another call to read will then extract the next data object from the line buffer.14/01/19 UAH-CPE/EE 422/522 AM 8Extracting Data from the Line Buffer (cont’d)•TEXTIO provides overloaded read procedures to read data of types bit, bit_vector, boolean, character, integer, real, string, and time from buffer•Read formsread(pointer, value)read(pointer, value, good)–good is boolean that returns TRUE if the read is successful and FALSE if it is not–type and size of value determines which of the read procedures is called–character, strings, and bit_vectors within files of type text are not delimited by quotes14/01/19 UAH-CPE/EE 422/522 AM 9Writing to TEXTIO files•Call one or more write procedures to write data to a line buffer and then call writeline to write the line to a filevariable buffw : line;variable int1 : integer; variable bv8 : bit_vector(7 downto 0);...write(buffw, int1, right, 6); --right just., 6 ch. widewrite(buffw, bv8, right, 10); writeln(buffw, output_file);•Write parameters: 1) buffer pointer of type line, 2) a value of any acceptable type, 3) justification (left or right), and 4) field width (number of characters)14/01/19 UAH-CPE/EE 422/522 AM 10An Example•Procedure to read data from a file and store the data in a memory array•Format of the data in the file–address N commentsbyte1 byte2 ... byteN comments•address – 4 hex digits•N – indicates the number of bytes of code•bytei - 2 hex digits•each byte is separated by one space•the last byte must be followed by a space•anything following the last state will not be read and will be treated as a comment14/01/19 UAH-CPE/EE 422/522 AM 11An Example (cont’d)•Code sequence: an example –12AC 7 (7 hex bytes follow)AE 03 B6 91 C7 00 0C (LDX imm, LDA dir, STA ext)005B 2 (2 bytes follow)01 FC_•TEXTIO does not include read procedure for hex numbers–we will read each hex value as a string of charactersand then convert the string to an integer•How to implement conversion?•table lookup – constant named lookup is an array of integers indexed by characters in the range ‘0’ to ‘F’•this range includes the 23 ASCII characters:‘0’, ‘1’, ... ‘9’, ‘:’, ‘;’, ‘<‘, ‘=‘, ‘>’, ‘?’, ‘@’, ‘A’, ... ‘F’•corresponding values:0, 1, ... 9, -1, -1, -1, -1, -1, -1, -1, 10, 11, 12, 13, 14, 1514/01/19 UAH-CPE/EE 422/522 AM 12VHDL Code to Fill Memory Array14/01/19 UAH-CPE/EE 422/522 AM 13VHDL Code to Fill Memory Array (cont’d)14/01/19 UAH-CPE/EE 422/522 AM 14Things to Remember•Attributes associated to signals –allow checking for setup, hold times, and other timing specifications•Attributes associated to arrays–allow us to write procedures that do not depend on the manner in which arrays are indexed•Inertial and transport delays–allow modeling of different delay types that occur in real systems•Operator overloading–allow us to extend the definition of VHDL operators so that they can be used with different types of operands14/01/19 UAH-CPE/EE 422/522 AM 15Things to Remember (cont’d)•Multivalued logic and the associated resolution functions–allow us to model tri-state buses, and systems where a signal is driven by more than one