Unformatted text preview:

CPE/EE 422/522 Advanced Logic Design L02OutlineReview: Combinational-Circuit Building BlocksMultiplexers: 2-to-1 MultiplexerReview: Synthesis of Logic Functions Using MuxesDecoders: n-to-2n DecoderDecoders: 2-to-4 DecoderEncodersEncoders: 4-to-2 EncoderEncoders: Priority EncodersCode ConvertersHazards in Combinational NetworksSlide 13Hazards in Combinational CircuitsSlide 15Programmable Logic DevicesRead-Only MemoriesBasic ROM StructureROM TypesProgrammable Logic Arrays (PLAs)PLA: 3 inputs, 5 p.t., 4 outputsnMOS NOR GateAND-OR Array EquivalentModified Truth Table for PLAUsing PLA: An ExampleSlide 26Slide 27Programmable Array Logic (PALs)Slide 29PALsLogic Diagram for 16R4 PALSlide 32Using PALs: An ExampleSlide 34Typical PALsTo DoSequential NetworksClocked D Flip-Flop with Rising-edge TriggerClocked JK Flip-FlopSlide 40S-R LatchTransparent D LatchSlide 43Mealy Sequential NetworksAn Example: 8421 BCD to Excess3 BCD Code ConverterState Graph and Table for Code ConverterState Assignment RulesTransition TableK-mapsRealizationCPE/EE 422/522Advanced Logic DesignL02Electrical and Computer EngineeringUniversity of Alabama in Huntsville01/14/19 UAH-CPE/EE 422/522 AM 2Outline•What we know–Laws and Theorems of Boolean Algebra–Simplification of Logic Expressions•Using Laws and Theorems of Boolean Algebra or Using K-maps–Design Using only NAND or only NOR gates–Tri-state buffers–Basic Combinational Building Blocks•Multiplexers, Decoders, Encoders, ...•What we do not know–Hazards in Combinational Networks–How to implement functions using ROMs, PLAs, and PALs–Sequential Networks (if time)01/14/19 UAH-CPE/EE 422/522 AM 3Review:Combinational-Circuit Building Blocks•Multiplexers•Decoders•Encoders•Code Converters•Comparators•Adders/Subtractors•Multipliers•Shifters01/14/19 UAH-CPE/EE 422/522 AM 4Multiplexers: 2-to-1 Multiplexer•Have number of data inputs, one or more select inputs, and one output–It passes the signal value on one of data inputs to the output(a) Graphical symbolfsw0w101fsw0w1(c) Sum-of-products circuit(b) Truth table01fsw0w110sww'sf 01/14/19 UAH-CPE/EE 422/522 AM 5Review:Synthesis of Logic Functions Using Muxesw3w3fw10w21(a) Modified truth table (b) Circuit00011101fw10w210 00 11 01 100010 00 11 01 10111w1w2w3f00001111w301/14/19 UAH-CPE/EE 422/522 AM 6Decoders: n-to-2n Decoder•Decode encoded information: n inputs, 2n outputs•If En = 1, only one output is asserted at a time•One-hot encoded output–m-bit binary code where exactly one bit is set to 10 w n 1 – n inputsEnEnable2 n outputs y 0 y 2 n 1 – w Enww...wy...En'ww'...wyEnw'w'...wyEn'w'w'...wynnnnn0111201120111011001/14/19 UAH-CPE/EE 422/522 AM 7Decoders: 2-to-4 Decoder0 0 1 1 1 0 1 y 0 w 1 0 w 0 (c) Logic circuit w 1 w 0 x x 1 1 0 1 1 En0 0 0 1 0 y 1 1 0 0 0 0 y 2 0 1 0 0 0 y 3 0 0 1 0 0 y 0 y 1 y 2 y 3 Enw 0 Eny 0 w 1 y 1 y 2 y 3 (a) Truth table (b) Graphic symbol01/14/19 UAH-CPE/EE 422/522 AM 8Encoders•Opposite of decoders–Encode given information into a more compact form•Binary encoders–2n inputs into n-bit code–Exactly one of the input signals should have a value of 1,and outputs present the binary number that identifies which input is equal to 1 •Use: reduce the number of bits (transmitting and storing information)2 n inputsw 0 w 2 n 1 – y 0 y n 1 – n outputs01/14/19 UAH-CPE/EE 422/522 AM 9Encoders: 4-to-2 Encoder0 0 1 1 1 0 1 w 3 y 1 0 y 0 (b) Circuit w 1 w 0 0 0 1 0 w 2 0 1 0 0 w 1 1 0 0 0 w 0 0 0 0 1 y 0 w 2 w 3 y 1 (a) Truth table01/14/19 UAH-CPE/EE 422/522 AM 10Encoders: Priority Encoders•Each input has a priority level associated with it•The encoder outputs indicate the active inputthat has the highest priorityd001010w0y1dy01 101111z1xx0xw101x0xw20010xw300001(a) Truth table for a 4-to-2 priority encoder01/14/19 UAH-CPE/EE 422/522 AM 11Code Converters•Convert from one type of input encoding to a different output encoding–E. g., BCD-to-7-segment decoderc e (a) Code converterw 0 a w 1 b c d w 2 w 3 e f g a g b f d (b) 7-segment display 1 0 1 1 1 1 1 w 0 a 1 b 0 1 1 1 1 0 1 1 0 1 0 0 w 1 0 1 1 0 0 w 2 0 0 0 0 1 w 3 0 0 0 0 0 c 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 d 0 1 0 0 1 0 e 1 0 1 1 1 0 1 0 0 1 0 0 0 1 f 1 0 0 1 1 1 g 1 0 1 1 1 1 1 1 0 1 (c) Truth table01/14/19 UAH-CPE/EE 422/522 AM 12Hazards in Combinational Networks•What are hazards in CM?–Unwanted switching transients at the output (glitches)•Example–ABC = 111, B changes to 0–Assume each gate has propagation delay of 10ns01/14/19 UAH-CPE/EE 422/522 AM 13Hazards in Combinational Networks•Occur when different paths from input to output have different propagation delays•Static 1-hazard –a network output momentarily go to the 0 when it should remain a constant 1•Static 0-hazard –a network output momentarily go to the 1 when it should remain a constant 0•Dynamic hazard–if an output change three or more times, when the output is supposed to change from 0 to 1 (1 to 0)01/14/19 UAH-CPE/EE 422/522 AM 14Hazards in Combinational Circuits1 1 1 1 0001111001ABCBC'ABf 1 1 1 1 0001111001ABCACBC'ABf To avoid hazards: every par of adjacent 1s should be covered by a 1-term01/14/19 UAH-CPE/EE 422/522 AM 15Hazards in Combinational CircuitsWhy do we care about hazards?•Combinational networks –don’t care – the network will function correctly•Synchronous sequential networks–don’t care - the input signals must be stable within setup and hold time of flip-flops•Asynchronous sequential networks–hazards can cause the network to enter an incorrect state–circuitry that generates the next-state variables must be hazard-free•Power consumption is proportional to the number of transitions01/14/19 UAH-CPE/EE 422/522 AM 16Programmable Logic Devices•Read Only Memories (ROMs)•Programmable Logic Arrays (PLAs)•Programmable Array Logic Devices (PALs)01/14/19 UAH-CPE/EE 422/522 AM 17Read-Only Memories•Store binary data–data can be read out whenever desired–cannot be changed under normal operating conditions•n input lines, m output lines => array of 2n m-bit words–Input lines serve as an address to select one of 2n words•Use ROM to implement logic functions?–n variables, m functions01/14/19 UAH-CPE/EE 422/522 AM 18Basic ROM Structure01/14/19 UAH-CPE/EE 422/522 AM 19ROM Types•Mask-programmable ROM –Data is permanently


View Full Document
Download Advanced Logic Design
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Advanced Logic Design and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Advanced Logic Design 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?