CPE/EE 422/522 Advanced Logic Design L05OutlineReview: Mealy Sequential NetworksReview: General Model of Moore Sequential MachineIntro to VHDLSlide 6VHDL Description of Combinational NetworksEntity-Architecture PairVHDL Program Structure4-bit Adder4-bit Adder (cont’d)4-bit Adder - SimulationModeling Flip-Flops Using VHDL ProcessesConcurrent Statements vs. ProcessD Flip-flop ModelJK Flip-Flop ModelSlide 17Using Nested IFs and ELSEIFsVHDL Models for a MUXMUX Models (1)MUX Models (2)MUX Models (3)MUX Models (4)Compilation and Simulation of VHDL CodeTiming ModelDelay TypesTransport DelayInertial DelayInertial Delay (cont.)Delta DelaySimulation ExampleProblem #1Problem #2Modeling a Sequential MachineBehavioral VHDL ModelSimulation of the VHDL ModelDataflow VHDL ModelStructural ModelSimulation of the Structural ModelWait StatementsForms of Wait StatementsUsing Wait Statements (1)Using Wait Statements (2)To DoCPE/EE 422/522Advanced Logic DesignL05Electrical and Computer EngineeringUniversity of Alabama in Huntsville01/14/19 UAH-CPE/EE 422/522 AM 2Outline•What we know–Combinational Networks–Sequential Networks: •Basic Building Blocks, Mealy & Moore Machines, Max Frequency, Setup & Hold Times, Synchronous Design•What we do not know–Equivalent states and reduction of state tables–Hardware Description Languages01/14/19 UAH-CPE/EE 422/522 AM 3Review: Mealy Sequential NetworksGeneral model of Mealy Sequential Network(1) X inputs are changed to a new value(2) After a delay, the Z outputs and next state appear at the output of CM(3) The next state is clocked into the state register and the state changes01/14/19 UAH-CPE/EE 422/522 AM 4Review: General Model of Moore Sequential Machine))t(Q(F)t(Z Inputs(X)ClockZ = z1 z2... zmX = x1 x2... xnQ = Q1 Q2... Qk))t(Q),t(X(G)t(Q Combinational NetworkState RegisterNext StateOutputs depend only on present state!Outputs(Z)State(Q)Combinational Network01/14/19 UAH-CPE/EE 422/522 AM 5Intro to VHDL•Technology trends–1 billion transistor chip running at 20 GHz in 2007•Need for Hardware Description Languages–Systems become more complex–Design at the gate and flip-flop level becomes very tedious and time consuming•HDLs allow–Design and debugging at a higher level before conversion to the gate and flip-flop level–Tools for synthesis do the conversion•VHDL, Verilog•VHDL – VHSIC Hardware Description Language01/14/19 UAH-CPE/EE 422/522 AM 6Intro to VHDL•Developed originally by DARPA–for specifying digital systems •International IEEE standard (IEEE 1076-1993)•Hardware Description, Simulation, Synthesis•Provides a mechanism for digital design and reusable design documentation•Support different description levels–Structural (specifying interconnections of the gates), –Dataflow (specifying logic equations), and –Behavioral (specifying behavior)•Top-down, Technology Dependent01/14/19 UAH-CPE/EE 422/522 AM 7VHDL Description of Combinational Networks01/14/19 UAH-CPE/EE 422/522 AM 8Entity-Architecture PairFull Adder Example01/14/19 UAH-CPE/EE 422/522 AM 9VHDL Program Structure01/14/19 UAH-CPE/EE 422/522 AM 104-bit Adder01/14/19 UAH-CPE/EE 422/522 AM 114-bit Adder (cont’d)01/14/19 UAH-CPE/EE 422/522 AM 124-bit Adder - Simulation01/14/19 UAH-CPE/EE 422/522 AM 13Modeling Flip-Flops Using VHDL Processes•Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time General form of process01/14/19 UAH-CPE/EE 422/522 AM 14Concurrent Statements vs. ProcessSimulation ResultsA, B, C, D are integersA=1, B=2, C=3, D=0D changes to 4 at time 10time delta A B C D0 +0 0 1 2 010 +0 1 2 3 4 (stat. 3 exe.)10 +1 1 2 4 4 (stat. 2 exe.)10 +2 1 4 4 4 (stat. 1 exe.)10 +3 4 4 4 4 (no exec.)01/14/19 UAH-CPE/EE 422/522 AM 15D Flip-flop ModelBit values are enclosed in single quotes01/14/19 UAH-CPE/EE 422/522 AM 16JK Flip-Flop Model01/14/19 UAH-CPE/EE 422/522 AM 17JK Flip-Flop Model01/14/19 UAH-CPE/EE 422/522 AM 18Using Nested IFs and ELSEIFs01/14/19 UAH-CPE/EE 422/522 AM 19VHDL Models for a MUXSel represents the integerequivalent of a 2-bit binary number with bits A and BIf a MUX model is used inside a process, the MUX can be modeled using a CASE statement(cannot use a concurrent statement):01/14/19 UAH-CPE/EE 422/522 AM 20MUX Models (1)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL1 of SELECTOR isbegin p0 : process (A, SEL) begin if (SEL = "0000") then Y <= A(0); elsif (SEL = "0001") then Y <= A(1); elsif (SEL = "0010") then Y <= A(2); elsif (SEL = "0011") then Y <= A(3); elsif (SEL = "0100") then Y <= A(4); elsif (SEL = "0101") then Y <= A(5); elsif (SEL = "0110") then Y <= A(6); elsif (SEL = "0111") then Y <= A(7); elsif (SEL = "1000") then Y <= A(8); elsif (SEL = "1001") then Y <= A(9); elsif (SEL = "1010") then Y <= A(10); elsif (SEL = "1011") then Y <= A(11); elsif (SEL = "1100") then Y <= A(12); elsif (SEL = "1101") then Y <= A(13); elsif (SEL = "1110") then Y <= A(14); else Y <= A(15); end if; end process;end RTL1;01/14/19 UAH-CPE/EE 422/522 AM 21MUX Models (2)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL3 of SELECTOR isbegin with SEL select Y <= A(0) when "0000", A(1) when "0001", A(2) when "0010", A(3) when "0011", A(4) when "0100", A(5) when "0101", A(6) when "0110", A(7) when "0111", A(8) when "1000", A(9) when "1001", A(10) when "1010", A(11) when "1011", A(12) when "1100", A(13) when "1101", A(14) when "1110", A(15) when others; end RTL3;01/14/19 UAH-CPE/EE 422/522 AM 22MUX Models (3)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL2 of SELECTOR isbegin p1 :