CPE EE 422 522 Advanced Logic Design L04 Electrical and Computer Engineering University of Alabama in Huntsville Outline What we know Combinational Networks Analysis Synthesis Simplification Hazards Building Blocks PALs PLAs ROMs Sequential Networks Basic Building Blocks Design Mealy Setup and hold times Max clock frequency What we do not know 01 14 19 Design Moore Equivalent States State Table Reduction Intro to VHDL UAH CPE EE 422 522 AM 2 Review Mealy Sequential Networks General model of Mealy Sequential Network 1 X inputs are changed to a new value 2 After a delay the Z outputs and next state appear at the output of CM 3 The next state is clocked into the state register and the state changes 01 14 19 UAH CPE EE 422 522 AM 3 Review 8421 BCD to Excess3 BCD Code Converter x Q 01 14 19 z X inputs Z outputs t3 t2 t1 t0 t3 t2 t1 t0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 UAH CPE EE 422 522 AM 4 Sequential Network Timing cont d Timing diagram assuming a propagation delay of 10 ns for each flip flop and gate State has been replaced with the state of three flip flops 01 14 19 UAH CPE EE 422 522 AM 5 Setup and Hold Times For a real D FF D input must be stable for a certain amount of time before the active edge of clock cycle Setup time D input must be stable for a certain amount of time after the active edge of the clock Hold time Propagation time from the time the clock changes to the time the output changes Manufacturers provide minimum tsu th and maximum tplh tphl 01 14 19 UAH CPE EE 422 522 AM 6 Maximum Clock Frequency t c max Max propagation delay through the combinational network t p max Max propagation delay from the time the clock changes to the flip flop output changes max tplh tphl t ck Clock period t c max t p max t ck t su t ck t c max t p max t su Example t p max 15 ns t su 5 ns t gate 15 ns t ck 2 15 15 5 50 ns fmax 01 14 19 UAH CPE EE 422 522 AM 1 20 MHz 50 ns 7 Hold Time Violation Occur if the change in Q fed back through the combinational network and cause D to change too soon after the clock edge Hold time is satisfied if t p min t c min t h What about X Make sure that input changes propagate to the flip flops inputs such that setup time is satisfied t x t cx max t su Make sure that X does not change too soon after the clock If X changes at time ty after the active edge hold time is satisfied if t y t h t cx min 01 14 19 UAH CPE EE 422 522 AM 8 Moore Sequential Networks Outputs depend only on present state x1 x2 X x1 x2 xn Q Q1 Q2 Qk Z z1 z2 zm Q xn z1 z2 zm Z t F Q t Q t G X t Q t 01 14 19 UAH CPE EE 422 522 AM 9 General Model of Moore Sequential Machine Outputs depend only on present state Combinational Network Inputs X Combinational Network Next State State Register Outputs Z State Q Clock X x1 x2 xn Q Q1 Q2 Qk Z z1 z2 zm 01 14 19 Q t G X t Q t Z t F Q t UAH CPE EE 422 522 AM 10 Code Converter Moore Machine Start 0 NC NC S1 1 NC 0 0 0 01 14 19 S6 0 1 S3 1 C NC S9 0 0 1 1 1 C 0 0 S0 0 NC 0 S7 1 NC S10 1 1 0 S4 0 1 1 C 0 C 0 S8 0 UAH CPE EE 422 522 AM S2 0 S5 1 1 1 1 11 Code Converter Moore Machine Start 0 NC NC S1 1 0 0 0 S6 0 1 S3 1 C NC S9 0 0 S4 0 0 1 1 1 C 0 0 NC S0 0 NC 0 S7 1 NC S10 1 1 1 S2 0 1 C 0 S5 1 1 C 0 S8 0 1 1 Do we need state S0 How many states does Moore machine have How many states does Mealy machine have 01 14 19 UAH CPE EE 422 522 AM 12 Moore Machine State Table Start 0 PS NS Z NC X 0 X 1 S0 S1 S2 0 S1 S3 S4 1 NC S2 S4 S5 0 0 S3 S6 S7 1 S4 S7 S8 0 S5 S7 S8 S9 S10 0 S7 S9 S10 1 S8 S10 0 S9 S1 S2 0 S10 S1 S2 1 0 S6 0 0 0 1 S6 01 14 19 NC NC S9 0 S1 1 S0 0 C 0 1 S3 1 C 0 1 1 1 NC 0 S7 1 NC S10 1 1 0 S4 0 1 S2 0 1 C 0 S5 1 1 C 0 S8 0 1 1 Note state S0 could be eliminated S0 S9 if S9 was start state UAH CPE EE 422 522 AM 13 Moore Machine Timing X 0010 1001 Z 1110 0011 Moore Mealy 01 14 19 UAH CPE EE 422 522 AM 14 State Assignments Guidelines to reduce the amount of combinational logic Rule I S0 S9 S10 S4 S5 S6 S7 Rule II S1 S2 S3 S4 S4 S5 S6 S7 S7 S8 S9 S10 Rule III S0 S2 S4 S6 S8 S9 Q1Q2 S1 S3 S5 S7 S10 01 00 Q3Q4 S0 0010 S1 0111 S10 0100 00 s10 10 S8 S5 01 11 10 01 14 19 S9 11 S0 S1 S3 S4 S2 S7 S6 UAH CPE EE 422 522 AM PS NS Z X 0 X 1 S0 S1 S2 0 S1 S3 S4 1 S2 S4 S5 0 S3 S6 S7 1 S4 S7 S8 0 S5 S7 S8 1 S6 S9 S10 0 S7 S9 S10 1 S8 S10 0 S9 S1 S2 0 S10 S1 S2 1 15 Moore Machine Another Example A Converter for Serial Data Transmission NRZ to Manchester Coding schemes for serial data transmission NRZ nonreturn to zero NRZI nonreturn to zero inverted 0 in input sequence the bit transmitted is the same as the previous bit 1 in input sequence transmit the complement of the previous bit RZ return to zero 0 0 for full bit time 1 1 for the first half 0 for the second half Manchester 01 14 …