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The University of Alabama in HuntsvilleECE DepartmentCourse SyllabusCPE 422/522 01Spring 2004Textbook: Digital Systems Design Using VHDL, Charles H. Roth, Jr., PWS Publishing, 1998(ISBN: 0-534-95099-X)Web Page: http://www.ece.uah.edu/courses/cpe422Instructor: Dr. Rhonda Kay Gaede, Office: EB 211, Phone: 824-6573,email: [email protected] Instructor: Mr. Zexin Pan, Office: EB 242D, Phone: 824-3483, email: [email protected] Hours: MW 2 PM — 3 PM, TR 4 PM — 5 PM, F 9 AM — 10 AM, or by appointmentGrading: Homework 10 %Lab Assignments 45 %Midterm Exam 15 %Final Exam 25 %Class Attendance 5 %Labs must be submitted at the beginning of the lab on the day they are due. Labssubmitted more than one week late will not be graded. Late labs will be penalized 20% for the first day late, and 10 % per day thereafter. No make-up exam will be givenunless you make arrangements with the (lab) instructor at least 24 hours in advance.All requests for a re-grade must be submitted in writing within a week of theassignment being returned. No assignment will be re-graded after one week.Any test done in pen will lose 10 %.Attendance is calculated as follows: A student may miss up to 5 classes of the 28classes in the semester and still receive all 5 points from attendance. If a studentmisses 6 or more classes, they receive 0 attendance points.Lab Assignments: The laboratory assignment component of the grade will be composed of simulation,labs, practical exam, and, for graduate students, a separate graduate design project.SIMULATIONS represent small assignments, which utilize the ModelSim or Alterasimulators to demonstrate the functionality of the design. The LABS representcomplete digital designs, which are to be actually implemented on rapid prototypinghardware that is present in the Rapid Prototyping Laboratory (RPL). The practicalEXAM is a short exam which measures the student s ability to implement simpledesigns using the CAD tools. Graduate students will be given an additional graduateproject (GRAD). The instructor will supply a default graduate laboratory assignmentto the class. The assignment of credit for each of these components is shown below:CPE/EE 422 CPE/EE 5221. Simulation 75 points 60 points2. Lab #1 50 points 40 points3. Lab #2 75 points 60 points4. Lab #3 75 points 60 points5. Lab #4 100 points 80 points6. Lab Exam 75 points 60 points7. Graduate Project - 90 pointsHomework: Homework turned in one class period late will be graded for 50 % credit, homeworkturned in more than one class period late will receive 0 % credit. Homework turned in morethan 5 minutes into the class on the due date will incur a 5% deduction.Acadamic UAH is committed to the fundamental values of preserving academic honesty asHonesty: defined in the Student Handbook (7.III.A). The instructor reserves the right to utilizeelectronic means to help prevent plagiarism. Students agree that by taking this courseall assignments are subject to submission for textual similarity review to Turnitin.com.Assignments submitted to Turnitin.com will be included as source documents inTurnitin.com’s restricted access database solely for the purpose of detecting plagiarismin such documents. The terms that apply to the University’s use of the Turnitin.comservice, as well as additional information about the company, are described atwww.uah.edu/library/turnitin.Important Dates: January 16 — Last day to add a class and file a course repeatJanuary 19 — Martin Luther King HolidayJanuary 26 — Last day to withdraw with refundFebruary 9 — Last day to change from credit to auditMarch 22-27 — Spring BreakMarch 29 — Last day to withdrawApril 5 — Registration for Summer and Fall 2004 semesters beginsApril 13 — Honors Day — No ClassesApril 27 — Last TR classFinal Exam: May 4 — 8:00 AM — 10:30 AMMiscellaneous: Mute your cell phones before you come to class.Topics CoveredChapter 1 Review of Logic Design FundamentalsCombinational Logic, Boolean Algebra and Algebraic Simplification, Karnaugh Maps, Designingwith NAND and NOR Gates, Hazards in Combinational Networks, Flip-flops and Latches, MealySequential Network Design, Design of a Moore Sequential Network, Equivalent States andReduction of State Tables, Sequential Network Timing, Setup and Hold Times, SynchronousDesign, Tristate Logic and BussesChapter 2 Introduction to VHDLVHDL Description of Combinational Networks, Modeling Flip-flops Using VHDL Processes,VHDL Models for a Multiplexer, Compilation and Simulation of VHDL Code, Modeling aSequential Machine, Variables, Signals, and Constants, Arrays, VHDL Operators, VHDLFunctions, VHDL Procedures, Packages and Libraries, VHDL Model for a 74163 CounterChapter 3 Designing with Programmable Logic DevicesRead-only Memories, Programmable Logic Arrays (PLAs), Programmable Array Logic (PALs),Other Sequential Programmable Logic Devices (PLDs), Design of a Keypad ScannerChapter 4 Design of Networks for Arithmetic OperationsState Graphs for Control Networks, Design of a Binary Multiplier,Chapter 5 Digital Design With SM ChartsState Machine Charts, Derivation of SM Charts, Realization of SM Charts, Implementation of theDice GameChapter 6 Designing With Programmable Gate Arrays and Complex Programmable LogicDevicesXilinx 3000 Series FPGAs, Designing with FPGAs, Xilinx 4000 Series FPGAs, Using a One-HotState Assignment, Altera Complex Programmable Logic Devices (CPLDs), Altera FLEX 10KSeries CPLDsChapter 8 Additional Topics in VHDLAttributes, Transport and Inertial Delays, Operator Overloading, Multivalued Logic and SignalResolution, IEEE-1164 Standard Logic, Generics, Generate Statements, Synthesis of VHDL Code,Synthesis Examples, Files and TEXTIOChapter 10 Hardware Testing and Design for TestabilityTesting Combinational Logic, Testing Sequential Logic, Scan Testing, Boundary Scan, Built-InSelf-TestTentative Course Schedule:Date TopicHomework Due1/13 T Introduction, 1.1, 1.21/15 R 1.3, 1.4, 1.131/20 T 3.1, 3.2, 3.31/22 R 1.6, 1.71/27 T 1.7, 1.8 #11/29 R 1.10, 1.11, 1.122/3 T 1.9, 1.5 #22.5 R 2.1, 2.22/10 T 2.3, 2.4 #32/12 R 2.4, 2.52/17 T 2.5, 2.6 #42/19 R 2.7, 2.82/24 T 2.9, 2.10 #52/26 R Midterm3/2 T 2.11, 2.123/4 R 3.4, 6.13/9 T 6.2 #63/11 R 6.33/16 T 6.4, 6.5 #73/18 R 6.63/23 T Spring Break — No Class3/25 R Spring Break — No Class3/30 T 8.1, 8.2, 8.34/1 R 8.4, 8.54/6 T 8.6, 8.7 #84/8 R 8.8, 8.94/13 T Honors Day — No Class4/15 R 4.2, 4.3, 5.1, 5.24/20 T 10.1, 10.2, 10.3 #94/22 R 10.4, 10.54/27 T Review5/4 T Final


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