CPE/EE 422/522 Advanced Logic Design L08OutlineReview: Modeling a Sequential MachineReview: Behavioral VHDL ModelReview: Wait StatementsReview: Forms of Wait StatementsReview: VariablesReview: SignalsReview: ConstantsReview: Variables vs. SignalsReview: Variables vs. Signals (cont’d)Predefined VHDL TypesUser Defined TypeArraysArrays (cont’d)Sequential Machine Model Using State TablePredefined Unconstrained Array TypesVHDL OperatorsExample of VHDL OperatorsExample of Shift OperatorsVHDL FunctionsFor LoopsAdd FunctionVHDL ProceduresProcedure for Adding Bit_vectorsParameters for Subprogram CallsPackages and LibrariesLibrary BITLIB – bit_pack packageSlide 29Slide 30VHDL Model for a 74163 CounterSlide 32Cascaded CountersCascaded Counters (cont’d)Additional Topics in VHDLSignal AttributesSignal Attributes (cont’d)Slide 38Slide 39Slide 40Examples of Signal AttributesUsing Attributes for Error CheckingArray AttributesRecap: Adding VectorsProcedure for Adding Bit VectorsTransport and Inertial DelayTransport and Inertial Delay (cont’d)Operator OverloadingVHDL Package with Overloaded OperatorsOverloaded OperatorsMultivalued LogicTristate BuffersSignal ResolutionSignal Resolution (cont’d)Resolution Function for X01ZAND and OR Functions Using X01ZIEEE 1164 Standard LogicResolution Function for IEEE 9-valuedAND Table for IEEE 9-valuedAND Function for std_logic_vectorsCPE/EE 422/522Advanced Logic DesignL08Electrical and Computer EngineeringUniversity of Alabama in Huntsville01/14/19 UAH-CPE/EE 422/522 AM 2Outline•What we know–How to model Combinational Networks in VHDL•Structural, Dataflow, Behavioral–How to model Flip-flops in VHDL–Processes–Delays (delta, transport, inertial)–How to model FSM in VHDL–Wait statements–Variables, Signals, Arrays•What we do not know–VHDL Operators–Procedures, Functions–Packages, Libraries–Additional Topics (if time)01/14/19 UAH-CPE/EE 422/522 AM 3Review: Modeling a Sequential MachineMealy Machine for 8421 BCD to 8421 BCD + 3 bit serial converterHow to model this in VHDL?01/14/19 UAH-CPE/EE 422/522 AM 4Review: Behavioral VHDL ModelTwo processes: •the first represents the combinational network;•the second represents the state register01/14/19 UAH-CPE/EE 422/522 AM 5Review: Wait Statements•... an alternative to a sensitivity list–Note: a process cannot have both wait statement(s)and a sensitivity list•Generic form of a process with wait statement(s)processbeginsequential-statementswait statementsequential-statementswait-statement...end process;How wait statements work?•Execute seq. statement until a wait statement is encountered.•Wait until the specified condition is satisfied.•Then execute the next set of sequential statements until the next wait statement is encountered.•...•When the end of the process is reached start over again at the beginning.01/14/19 UAH-CPE/EE 422/522 AM 6Review: Forms of Wait Statements•Wait on –until one of the signals in the sensitivity list changes•Wait for–waits until the time specified by the time expression has elapsed–What is this:wait for 0 ns;•Wait until–the boolean expression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUEwait on sensitivity-list;wait for time-expression;wait until boolean-expression;01/14/19 UAH-CPE/EE 422/522 AM 7Review: Variables•What are they for: Local storage in processes, procedures, and functions•Declaring variablesvariable list_of_variable_names : type_name [ := initial value ];•Variables must be declared within the process in which they are used and are local to the process–Note: exception to this is SHARED variables01/14/19 UAH-CPE/EE 422/522 AM 8Review: Signals•Signals must be declared outside a process•Declaration formsignal list_of_signal_names : type_name [ := initial value ];•Declared in an architecture can be used anywhere within that architecture01/14/19 UAH-CPE/EE 422/522 AM 9Review: Constants•Declaration formconstant constant_name : type_name := constant_value;•Constants declared at the start of an architecturecan be used anywhere within that architecture•Constants declared within a process are localto that processconstant delay1 : time := 5 ns;01/14/19 UAH-CPE/EE 422/522 AM 10Review: Variables vs. Signals•Variable assignment statementvariable_name := expression;•Signal assignment statementsignal_name <= expression [after delay];–expression is evaluated and the variable is instantaneously updated(no delay, not even delta delay)–expression is evaluated and the signal is scheduled to change after delay; if no delay is specified the signal is scheduled to be updated after a delta delay01/14/19 UAH-CPE/EE 422/522 AM 11Review: Variables vs. Signals (cont’d)Process Using VariablesProcess Using SignalsSum = ?Sum = ?01/14/19 UAH-CPE/EE 422/522 AM 12Predefined VHDL Types•Variables, signals, and constants can have any one of the predefined VHDL types or they can have a user-defined type•Predefined Types–bit – {‘0’, ‘1’}–boolean – {TRUE, FALSE}–integer – [-231 - 1.. 231 – 1}–real – floating point number in range –1.0E38 to +1.0E38–character – legal VHDL characters including lower- uppercase letters, digits, special characters, ...–time – an integer with units fs, ps, ns, us, ms, sec, min, or hr01/14/19 UAH-CPE/EE 422/522 AM 13User Defined Type•Common user-defined type is enumeratedtype state_type is (S0, S1, S2, S3, S4, S5); signal state : state_type := S1;•If no initialization, the default initialization is the leftmost element in the enumeration list (S0 in this example)•VHDL is strongly typed language =>signals and variables of different types cannot be mixed in the same assignment statement,and no automatic type conversion is performed01/14/19 UAH-CPE/EE 422/522 AM 14Arrays•Exampletype SHORT_WORD is array (15 downto 0) of bit; signal DATA_WORD : SHORT_WORD;variable ALT_WORD : SHORT_WORD := “0101010101010101”;constant ONE_WORD : SHORT_WORD := (others => ‘1’);•ALT_WORD(0) – rightmost bit•ALT_WORD(5 downto 0) – low order 6 bits•General formtype arrayTypeName is array index_range of element_type;signal arrayName : arrayTypeName [:=InitialValues];01/14/19 UAH-CPE/EE 422/522 AM 15Arrays (cont’d)•Multidimensional arraystype matrix4x3 is array (1 to 4, 1 to 3) of integer; variable matrixA: matrix4x3